AN 705: Scalable 10G Ethernet MAC using 1G/10G PHY

ID 683066
Date 5/13/2016
Public
Document Table of Contents

1.11. Register Map

MSA0 is a 32-bit memory space address that provides access to all the client logic and scalable 1G/10G design example configuration registers. All registers in this space are 32-bit registers. Access smaller than 32 bits are not supported.

Table 18.  Design Example Block Register MapThe following table shows the address offset for the design example and client logic at the design example level.
Byte Offset Block
0x00_0000 - 0x00_EFFF Client Logic
0x00_F000 - 0x00_FFFF 1G/10G Ethernet Reconfig Controller
0x01_0000 Master TOD
0x02_0000 Port 0
0x03_0000 Port 1
0x04_0000 Port 2
0x05_0000 Port 3
0x06_0000 Port 4
0x07_0000 Port 5
0x08_0000 Port 6
0x09_0000 Port 7
0x0A_0000 Port 8
0x0B_0000 Port 9
0x0C_0000 Port 10
0x0D_0000 Port 11
0x0E_0000 onwards Client Logic
Table 19.  Port Sub-block Register MapThe following table shows the address offset for the design example logic for each port.
Byte Offset Sub-Block
0x0000 - 0x6FFF Altera Logic
0x4000 PHY
0x7800 10G TOD
0x7900 1G TOD
0x8000 1G/10G MAC