AN 705: Scalable 10G Ethernet MAC using 1G/10G PHY

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ID 683066
Date 5/13/2016
Public
Document Table of Contents
Document Table of Contents x
1. Scalable 10G Ethernet MAC using 1G/10G PHY
1. Scalable 10G Ethernet MAC using 1G/10G PHY x
1.1. Features 1.2. Parameters 1.3. Block Diagrams 1.4. Components 1.5. Requirements 1.6. Design Example Walkthrough 1.7. Design Example Testbench 1.8. Clocking Scheme 1.9. Reset Scheme 1.10. Interface Signals 1.11. Register Map 1.12. Known Issues 1.13. Document Revision History
1.6. Design Example Walkthrough x
1.6.1. Setting Up the Design Examples 1.6.2. Changing Number of Channels 1.6.3. Configuring PHY Speed 1.6.4. IP Regeneration
1.6.3. Configuring PHY Speed x
1.6.3.1. Changing Speed between 10G and 1G in 1000BaseX mode 1.6.3.2. Changing Speed between 1G, 100M, and 10M SGMII
1.7. Design Example Testbench x
1.7.1. Testbench Components 1.7.2. Testbench Files 1.7.3. Simulating Testbench 1.7.4. Test Case
1.7.3. Simulating Testbench x
1.7.3.1. Using ModelSim Simulator 1.7.3.2. Using VCS Simulator
1.7.4. Test Case x
1.7.4.1. Test Scenario for Design Example without IEEE 1588v2 1.7.4.2. Test Scenario for Design Example with IEEE 1588v2
1.7.4.2. Test Scenario for Design Example with IEEE 1588v2 x
1.7.4.2.1. Testcase 1 1.7.4.2.2. Testcase 2 1.7.4.2.3. Testcase 3
1.8. Clocking Scheme x
1.8.1. Clocking Diagram 1.8.2. Sync-E Support
1.8.2. Sync-E Support x
1.8.2.1. Enable Ref Clock Sharing 1.8.2.2. Disable Ref Clock Sharing
1.9. Reset Scheme x
1.9.1. Design Example without IEEE 1588v2 1.9.2. Design Example with IEEE 1588v2 1.9.3. Internal PHY PLL Powerdown Connection Scheme
1.9.1. Design Example without IEEE 1588v2 x
1.9.1.1. Channel Level Reset Scheme 1.9.1.2. Multi-Channel Level Reset Scheme
1.9.2. Design Example with IEEE 1588v2 x
1.9.2.1. Channel Level Reset Scheme 1.9.2.2. Multi-Channel Level Reset Scheme
1.10. Interface Signals x
1.10.1. Clock and Reset Interface Signals 1.10.2. Avalon-MM Interface Signals 1.10.3. Avalon-ST Interface Signals 1.10.4. PHY Interface Signals 1.10.5. MDIO Interface Signals 1.10.6. IEEE 1588v2 Timestamp Interface Signals 1.10.7. Packet Classifier Interface Signals 1.10.8. ToD Interface Signals
1.11. Register Map x
1.11.1. Master TOD 1.11.2. 1G TOD 1.11.3. 10G TOD 1.11.4. PHY 1.11.5. 1G/10G MAC
1. Scalable 10G Ethernet MAC using 1G/10G PHY

1.11.4. PHY

PHY registers are applicable to both design examples.
Table 25.  Base Address of PHY Registers
Channel PHY Register Base Address
0 MSA0 + 0x02_4000
1 MSA0 + 0x03_4000
2 MSA0 + 0x04_4000
3 MSA0 + 0x05_4000
4 MSA0 + 0x06_4000
5 MSA0 + 0x07_4000
6 MSA0 + 0x08_4000
7 MSA0 + 0x09_4000
8 MSA0 + 0x0A_4000
9 MSA0 + 0x0B_4000
10 MSA0 + 0x0C_4000
11 MSA0 + 0x0D_4000
Note: For the description of each PHY register, refer to the Altera Transceiver PHY IP Core User Guide. The address offset in the following tables is in byte, while the register map table in the Altera Transceiver PHY IP Core User Guide is in word.
Table 26.  PMA Registers
Byte Offset Bit R/W Name
0x0088 RO pma_tx_pll_is_locked
0x0110 1 RW reset_tx_digital
2 RW reset_rx_analog
3 RW reset_rx_digital
0x0184 RW phy_serial_loopback
0x0190 RW pma_rx_set_locktodata
0x0194 RW pma_rx_set_locktoref
0x0198 RO pma_rx_is_lockedtodata
0x019C RO pma_rx_is_lockedtoref
0x02A0 0 RW tx_invpolarity
1 RW rx_invpolarity
2 RW rx_bitreversal_enable
3 RW rx_bytereversal_enable
4 RW force_electrical_idle
0x02A4 0 R rx_syncstatus
1 R rx_patterndetect
2 R rx_rlv
3 R rx_rmfifodatainserted
4 R rx_rmfifodatadeleted
5 R rx_disperr
6 R rx_errdetect
Table 27.  PCS Registers
Byte Offset Bit R/W Name
0x0200   RW Indirect_addr
0x0204 2 RW RCLR_ERRBLK_CNT
3 RW RCLR_BER_COUNT
0x0208 1 RO HI_BER
2 RO BLOCK_LOCK
3 RO TX_FULL
4 RO RX_FULL
5 RO RX_SYNC_HEAD_ERROR
6 RO RX_SCRAMBLER_ERROR
7 RO Rx_DATA_READY
Table 28.  1G/10GbE GMII PCS Registers
Byte Offset Bit R/W Name
0x0240 9 RW RESTART_AUTO_ NEGOTIATION
12 RW AUTO_NEGOTIATION_ ENABLE
15 RW Reset
0x0244 2 R LINK_STATUS
3 R AUTO_NEGOTIATION_ ABILITY
5 R AUTO_NEGOTIATION_ COMPLETE
0x0250 5 RW FD
6 RW HD
8:7 RW PS2,PS1
13:12 RW RF2,RF1
14 R0 ACK
15 RW NP
0x0254 5 R FD
6 R HD
8:7 R PS2,PS1
13:12 R RF2,RF1
14 R ACK
15 R NP
0x0258 0 R LINK_PARTNER_AUTO_NEGOTIATION_ABLE
1 R PAGE_RECEIVE
0x0288 15:0 RW AN link timer[15:0]
0x028C 4:0 RW AN link timer[4:0]
0x0290 0 RW SGMII_ENA
1 RW USE_SGMII_AN
3:2 RW SGMII_SPEED
Table 29.  1G/10GbE Register Definitions
Byte Offset Bit R/W Name
0x02C0 0 RW Reset SEQ
1 RW Disable AN Timer
2 RW Disable LF Timer
6:4 RW SEQ Force Mode[2:0]
16 RW FEC ability
18 RW FEC request
0x02C4 0 R SEQ Link Ready
1 R SEQ AN timeout
2 R SEQ LT timeout
13:8 RW SEQ Reconfig Mode[5:0]
16 R KR FEC ability
17 R KR FEC err ind ability
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