AN 705: Scalable 10G Ethernet MAC using 1G/10G PHY

ID 683066
Date 5/13/2016
Document Table of Contents

1.9.3. Internal PHY PLL Powerdown Connection Scheme

All transceiver reset input signals are connected to Transceiver(XCVR) Reset Controller in individual channel except pll_powerdown. pll_powerdown port of every transceiver channels are connected to master_reset_n. This setup enables all channels of the transceiver to be placed in contiguous banks and fewer ATX PLLs and CMU PLLs is used as they are being merged after fitter process.