AN 705: Scalable 10G Ethernet MAC using 1G/10G PHY

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ID 683066
Date 5/13/2016
Public
Document Table of Contents
Document Table of Contents x
1. Scalable 10G Ethernet MAC using 1G/10G PHY
1. Scalable 10G Ethernet MAC using 1G/10G PHY x
1.1. Features 1.2. Parameters 1.3. Block Diagrams 1.4. Components 1.5. Requirements 1.6. Design Example Walkthrough 1.7. Design Example Testbench 1.8. Clocking Scheme 1.9. Reset Scheme 1.10. Interface Signals 1.11. Register Map 1.12. Known Issues 1.13. Document Revision History
1.6. Design Example Walkthrough x
1.6.1. Setting Up the Design Examples 1.6.2. Changing Number of Channels 1.6.3. Configuring PHY Speed 1.6.4. IP Regeneration
1.6.3. Configuring PHY Speed x
1.6.3.1. Changing Speed between 10G and 1G in 1000BaseX mode 1.6.3.2. Changing Speed between 1G, 100M, and 10M SGMII
1.7. Design Example Testbench x
1.7.1. Testbench Components 1.7.2. Testbench Files 1.7.3. Simulating Testbench 1.7.4. Test Case
1.7.3. Simulating Testbench x
1.7.3.1. Using ModelSim Simulator 1.7.3.2. Using VCS Simulator
1.7.4. Test Case x
1.7.4.1. Test Scenario for Design Example without IEEE 1588v2 1.7.4.2. Test Scenario for Design Example with IEEE 1588v2
1.7.4.2. Test Scenario for Design Example with IEEE 1588v2 x
1.7.4.2.1. Testcase 1 1.7.4.2.2. Testcase 2 1.7.4.2.3. Testcase 3
1.8. Clocking Scheme x
1.8.1. Clocking Diagram 1.8.2. Sync-E Support
1.8.2. Sync-E Support x
1.8.2.1. Enable Ref Clock Sharing 1.8.2.2. Disable Ref Clock Sharing
1.9. Reset Scheme x
1.9.1. Design Example without IEEE 1588v2 1.9.2. Design Example with IEEE 1588v2 1.9.3. Internal PHY PLL Powerdown Connection Scheme
1.9.1. Design Example without IEEE 1588v2 x
1.9.1.1. Channel Level Reset Scheme 1.9.1.2. Multi-Channel Level Reset Scheme
1.9.2. Design Example with IEEE 1588v2 x
1.9.2.1. Channel Level Reset Scheme 1.9.2.2. Multi-Channel Level Reset Scheme
1.10. Interface Signals x
1.10.1. Clock and Reset Interface Signals 1.10.2. Avalon-MM Interface Signals 1.10.3. Avalon-ST Interface Signals 1.10.4. PHY Interface Signals 1.10.5. MDIO Interface Signals 1.10.6. IEEE 1588v2 Timestamp Interface Signals 1.10.7. Packet Classifier Interface Signals 1.10.8. ToD Interface Signals
1.11. Register Map x
1.11.1. Master TOD 1.11.2. 1G TOD 1.11.3. 10G TOD 1.11.4. PHY 1.11.5. 1G/10G MAC
1. Scalable 10G Ethernet MAC using 1G/10G PHY

1.6.4. IP Regeneration

Regeneration of IP files is required when upgrading to a new version of ACDS. This process involves 2 different tools: Qsys and Megawizard. The following table shows the IPs that need regeneration and the tools involved.
Table 5.  List of IPs Require Regeneration
IP Tools IP File Locations
address_decoder_channel Qsys ADDRESS_DECODER/address_decoder_channel.qsys
address_decoder_multi_channel Qsys ADDRESS_DECODER/address_decoder_multi_channel.qsys
address_decoder_top Qsys ADDRESS_DECODER/address_decoder_top.qsys
altera_eth_1588_tod1 Qsys altera_eth_1588_tod/altera_eth_1588_tod.qsys
altera_eth_1588_tod_synchronizer 1 Qsys altera_eth_1588_tod_synchronizer/ altera_eth_1588_tod_synchronizer.qsys
altera_eth_packet_classifier1 Qsys altera_eth_packet_classifier/ altera_eth_packet_classifier.qsys
altera_eth_10g_mac Megawizard
  • Without IEEE 1588v2: MAC/altera_eth_10g_mac.v
  • With IEEE 1588v2: MAC_W_1588/altera_eth_10g_mac.v
altera_eth_10gkr_phy Megawizard
  • Without IEEE 1588v2: PHY/altera_eth_10gkr_phy.v
  • With IEEE 1588v2: PHY_W_1588/altera_eth_10gkr_phy.v
altera_xcvr_reset_controller Megawizard XCVR_RESET_CONTROLLER/altera_xcvr_reset_controller.v
reconfig Megawizard RECONFIG/reconfig.v
pll Megawizard PLL/pll.v
pll_2 1 Megawizard PLL/pll_2.v

Launch the tool and open the IP files listed in the table to regenerate the IP.

1 This IP is only available for design example with IEEE 1588v2.
Level Two Title