AN 705: Scalable 10G Ethernet MAC using 1G/10G PHY

ID 683066
Date 5/13/2016
Document Table of Contents
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1.3. Block Diagrams

Figure 1.  Block Diagram for Design Example without IEEE 1588v2
Figure 2.  Block Diagram for Design Example with IEEE 1588v2 You can use one of the following module:
  • altera_eth_multi_channel_1588_wrapper—includes address_decoder_multi_channel block which consolidate address_decoder_channel of all channels and Master TOD into a single Avalon-MM interface.
  • altera_eth_multi_channel_1588—exposes Avalon-MM interface of address_decoder_channel of every channels and Master TOD to provide more flexible access and register map address space allocation.