AN 705: Scalable 10G Ethernet MAC using 1G/10G PHY

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ID 683066
Date 5/13/2016
Public
Document Table of Contents
Document Table of Contents x
1. Scalable 10G Ethernet MAC using 1G/10G PHY
1. Scalable 10G Ethernet MAC using 1G/10G PHY x
1.1. Features 1.2. Parameters 1.3. Block Diagrams 1.4. Components 1.5. Requirements 1.6. Design Example Walkthrough 1.7. Design Example Testbench 1.8. Clocking Scheme 1.9. Reset Scheme 1.10. Interface Signals 1.11. Register Map 1.12. Known Issues 1.13. Document Revision History
1.6. Design Example Walkthrough x
1.6.1. Setting Up the Design Examples 1.6.2. Changing Number of Channels 1.6.3. Configuring PHY Speed 1.6.4. IP Regeneration
1.6.3. Configuring PHY Speed x
1.6.3.1. Changing Speed between 10G and 1G in 1000BaseX mode 1.6.3.2. Changing Speed between 1G, 100M, and 10M SGMII
1.7. Design Example Testbench x
1.7.1. Testbench Components 1.7.2. Testbench Files 1.7.3. Simulating Testbench 1.7.4. Test Case
1.7.3. Simulating Testbench x
1.7.3.1. Using ModelSim Simulator 1.7.3.2. Using VCS Simulator
1.7.4. Test Case x
1.7.4.1. Test Scenario for Design Example without IEEE 1588v2 1.7.4.2. Test Scenario for Design Example with IEEE 1588v2
1.7.4.2. Test Scenario for Design Example with IEEE 1588v2 x
1.7.4.2.1. Testcase 1 1.7.4.2.2. Testcase 2 1.7.4.2.3. Testcase 3
1.8. Clocking Scheme x
1.8.1. Clocking Diagram 1.8.2. Sync-E Support
1.8.2. Sync-E Support x
1.8.2.1. Enable Ref Clock Sharing 1.8.2.2. Disable Ref Clock Sharing
1.9. Reset Scheme x
1.9.1. Design Example without IEEE 1588v2 1.9.2. Design Example with IEEE 1588v2 1.9.3. Internal PHY PLL Powerdown Connection Scheme
1.9.1. Design Example without IEEE 1588v2 x
1.9.1.1. Channel Level Reset Scheme 1.9.1.2. Multi-Channel Level Reset Scheme
1.9.2. Design Example with IEEE 1588v2 x
1.9.2.1. Channel Level Reset Scheme 1.9.2.2. Multi-Channel Level Reset Scheme
1.10. Interface Signals x
1.10.1. Clock and Reset Interface Signals 1.10.2. Avalon-MM Interface Signals 1.10.3. Avalon-ST Interface Signals 1.10.4. PHY Interface Signals 1.10.5. MDIO Interface Signals 1.10.6. IEEE 1588v2 Timestamp Interface Signals 1.10.7. Packet Classifier Interface Signals 1.10.8. ToD Interface Signals
1.11. Register Map x
1.11.1. Master TOD 1.11.2. 1G TOD 1.11.3. 10G TOD 1.11.4. PHY 1.11.5. 1G/10G MAC
1. Scalable 10G Ethernet MAC using 1G/10G PHY

1.7.4.2.2. Testcase 2

This testcase simulates manual speed change between 10G/1G/100M/10M in SGMII/1000Base-X mode with auto negotiation disabled using serial loopback configuration.

  • To choose speed for each channel, go to tb_testcase_1588, change the value of reg [1:0] speed[NUM_CHANNELS] = {}
  • To change number of channels: modify the parameter NUM_CHANNELS in default_test_parameter.sv file
  • To choose SGMII or 1000 Base-X mode for 1G, go to default_test_parameter.sv file, change parameter SGMII_1000BASEX (1-SGMII, 0-1000 Base-X)
  • PHY serial loopback for each channel setup:
    • channel0: 10G
    • channel1: 1G
    • channel2: 100M
    • channel3: 10M
Figure 9. Waveform for Channel_ready and speed_sel for All 4 Channels
  1. Force the channel0 to 10G mode and the data transmission can be observed in XGMII interface.
  2. Force the channel1 to 1G mode and the data transmission can be observed in GMII interface.
  3. To set channel2 to 100M mode, first set the channel to 1G mode. Next, enable the SGMII mode and set it to 100M mode. Data transmission can be observed in MII interface signals.
  4. Repeat Step 3 for channel3, only this time set the speed to 10M after enabling SGMII mode. Data transmission can be observed in MII interface signals.
  5. The data transmission for each channel will only start when the channel_ready signal is up. MAC TX and RX statistic will be printed out in transcript window for each channel.
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