AN 705: Scalable 10G Ethernet MAC using 1G/10G PHY

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ID 683066
Date 5/13/2016
Public
Document Table of Contents
Document Table of Contents x
1. Scalable 10G Ethernet MAC using 1G/10G PHY
1. Scalable 10G Ethernet MAC using 1G/10G PHY x
1.1. Features 1.2. Parameters 1.3. Block Diagrams 1.4. Components 1.5. Requirements 1.6. Design Example Walkthrough 1.7. Design Example Testbench 1.8. Clocking Scheme 1.9. Reset Scheme 1.10. Interface Signals 1.11. Register Map 1.12. Known Issues 1.13. Document Revision History
1.6. Design Example Walkthrough x
1.6.1. Setting Up the Design Examples 1.6.2. Changing Number of Channels 1.6.3. Configuring PHY Speed 1.6.4. IP Regeneration
1.6.3. Configuring PHY Speed x
1.6.3.1. Changing Speed between 10G and 1G in 1000BaseX mode 1.6.3.2. Changing Speed between 1G, 100M, and 10M SGMII
1.7. Design Example Testbench x
1.7.1. Testbench Components 1.7.2. Testbench Files 1.7.3. Simulating Testbench 1.7.4. Test Case
1.7.3. Simulating Testbench x
1.7.3.1. Using ModelSim Simulator 1.7.3.2. Using VCS Simulator
1.7.4. Test Case x
1.7.4.1. Test Scenario for Design Example without IEEE 1588v2 1.7.4.2. Test Scenario for Design Example with IEEE 1588v2
1.7.4.2. Test Scenario for Design Example with IEEE 1588v2 x
1.7.4.2.1. Testcase 1 1.7.4.2.2. Testcase 2 1.7.4.2.3. Testcase 3
1.8. Clocking Scheme x
1.8.1. Clocking Diagram 1.8.2. Sync-E Support
1.8.2. Sync-E Support x
1.8.2.1. Enable Ref Clock Sharing 1.8.2.2. Disable Ref Clock Sharing
1.9. Reset Scheme x
1.9.1. Design Example without IEEE 1588v2 1.9.2. Design Example with IEEE 1588v2 1.9.3. Internal PHY PLL Powerdown Connection Scheme
1.9.1. Design Example without IEEE 1588v2 x
1.9.1.1. Channel Level Reset Scheme 1.9.1.2. Multi-Channel Level Reset Scheme
1.9.2. Design Example with IEEE 1588v2 x
1.9.2.1. Channel Level Reset Scheme 1.9.2.2. Multi-Channel Level Reset Scheme
1.10. Interface Signals x
1.10.1. Clock and Reset Interface Signals 1.10.2. Avalon-MM Interface Signals 1.10.3. Avalon-ST Interface Signals 1.10.4. PHY Interface Signals 1.10.5. MDIO Interface Signals 1.10.6. IEEE 1588v2 Timestamp Interface Signals 1.10.7. Packet Classifier Interface Signals 1.10.8. ToD Interface Signals
1.11. Register Map x
1.11.1. Master TOD 1.11.2. 1G TOD 1.11.3. 10G TOD 1.11.4. PHY 1.11.5. 1G/10G MAC
1. Scalable 10G Ethernet MAC using 1G/10G PHY

1.6.1. Setting Up the Design Examples

To set up the design examples, follow these steps:

  1. Unzip and untar the design examples at the project directory.
    Note:

    Altera recommends you to untar the example design in Linux environment. The VCS simulation script may become unrecognized or non-executable if the project archive was unzip in Windows environment.

  2. Launch the Quartus II software and open the following project file:

    • altera_eth_1g10g_top.qpf—for Scalable Multispeed 10G Ethernet MAC using 1G/10G PHY without IEEE 1588v2.

    • altera_eth_top.qpf—for Scalable Multispeed 10G Ethernet MAC using 1G/10G PHY with IEEE 1588v2.

  3. Click Start Compilation on the Processing menu to compile the design example.
  4. Configure the FPGA on Stratix V GX Transceiver SI Development Board using either:
    • altera_eth_1g10g_top.sof—for Scalable Multispeed 10G Ethernet MAC using 1G/10G PHY without IEEE 1588v2.
    • altera_eth_top.sof—for Scalable Multispeed 10G Ethernet MAC using 1G/10G PHY with IEEE1588v2.
  5. After configuration is done, open the Clock Control tool from kits\stratixVGX_5sgxea7nf40_si\examples\board_test_system\ClockControl.exe
    The Clock Control tool that is shipped with the “Installation Kit” for Stratix V GX Transceiver SI Development Board.
  6. Set the new frequency for Y3 and Y4 as shown below:
    1. Y3: 322.265625 MHz
    2. Y4: 125.00MHz
    Figure 3. Clock Control Settings for Y3
    Figure 4. Clock Control Settings for Y4
  7. Press PB0 push button to reset the system.
    Note: System must be hard reset after configuration done.
  8. On Quartus II Tools menu, click on System Debugging Tools and then launch System Console.
  9. In the System Console command shell, change the directory to either:
    • SystemConsole_wo1588—for Scalable Multispeed 10G Ethernet MAC using 1G/10G PHY without IEEE 1588v2
    • SystemConsole—for Scalable Multispeed 10G Ethernet MAC using 1G/10G PHY with IEEE 1588v2
  10. Run the command source main.tcl to initialize the reference design command list.
  11. Perform the following test by running the command in the System Console command shell:
    1. PHY internal serial loopback
      Command: TEST_PHYSERIAL_LOOPBACK {channel speed_test burst_size}
      Example: TEST_PHYSERIAL_LOOPBACK 0 1G 1000
    2. SMA loopback
      Command:
      • TEST_SMA_LOOPBACK {channel speed_test burst_size}—for Scalable Multispeed 10G Ethernet MAC using 1G/10G PHY without IEEE 1588v2
        Note: Channel 1 is assigned to SFP+ by default. To test Channel 1, you need to reassign it to SMA port.
      • TEST_SMA_LB {channel speed_test burst_size}—for Scalable Multispeed 10G Ethernet MAC using 1G/10G PHY with IEEE 1588v2
      Example: TEST_SMA_LOOPBACK 0 1G 1000
    3. SMA loopback between 2 channels (for Scalable Multispeed 10G Ethernet MAC using 1G/10G PHY with IEEE 1588v2)
      Command: TEST_1588 {from_channel to_channel speed_test}
      Example: TEST_1588 0 1 1G
    Note:

    For Scalable Multispeed 10G Ethernet MAC using 1G/10G PHY without IEEE 1588v2, Channel 0 is assigned to SMA (GXB_RXL_17 & GXB_TXL_17) and Channel 1 is assigned to SFP+ by default.

    For Scalable Multispeed 10G Ethernet MAC using 1G/10G PHY with IEEE 1588v2, Channel 0 is assigned to SMA (GXB_RXL_17 & GXB_TXL_17) and Channel 1 is assigned to SMA (GXB_RXL_16 & GXB_TXL_16) by default.

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