AN 705: Scalable 10G Ethernet MAC using 1G/10G PHY

ID 683066
Date 5/13/2016
Document Table of Contents

1.11.5. 1G/10G MAC

MAC registers are applicable to both design examples.
Table 30.  Base Address of 1G/10G MAC Registers
Channel PHY Register Base Address
0 MSA0 + 0x02_8000
1 MSA0 + 0x03_8000
2 MSA0 + 0x04_8000
3 MSA0 + 0x05_8000
4 MSA0 + 0x06_8000
5 MSA0 + 0x07_8000
6 MSA0 + 0x08_8000
7 MSA0 + 0x09_8000
8 MSA0 + 0x0A_8000
9 MSA0 + 0x0B_8000
10 MSA0 + 0x0C_8000
11 MSA0 + 0x0D_8000
Note: For the description of each MAC register, refer to the 10-Gbps Ethernet MAC Megacore Function User Guide. The address offset in the following tables is in byte, while the register map table in the 10-Gbps Ethernet MAC Megacore Function User Guide is in word.
Table 31.  MAC Register Components and Offset Range
Component Byte Offset Range
RX Packet Transfer 0x0000:0x00FF
RX Pad/CRC Remover 0x0100:0x01FF
RX CRC Checker 0x0200:0x02FF
RX Packet Overflow 0x0300:0x03FF
RX Preamble Control 0x0400:0x04FF
RX Lane Decoder 0x0500:0x1FFF
RX Frame Decoder 0x2000:0x2FFF
RX Statistics Counters 0x3000:0x3FFF
TX Packet Transfer 0x4000:0x40FF
TX Pad Inserter 0x4100:0x41FF
TX CRC Inserter 0x4200:0x42FF
TX Packet Underflow 0x4300:0x43FF
TX Preamble Control 0x4400:0x44FF
TX Pause Frame Control and Generator 0x4500:0x45FF
TX PFC Generator 0x4600:0x47FF
TX Address Inserter 0x4800:0x5FFF
TX Frame Decoder 0x6000:0x6FFF
TX Statistics Counters 0x7000:0x7FFF
Table 32.  1G/10G MAC Registers for IEEE 1588v2 Feature
Register Byte Offset
rx_period 0x0440 (10G)
0x0460 (1G)
rx_adjust_fns 0x0448 (10G)
0x0468 (1G)
rx_adjust_ns 0x044C (10G)
0x046C (1G)
tx_period 0x4440 (10G)
0x4460 (1G)
tx_adjust_fns 0x4448 (10G)
0x4468 (1G)
tx_adjust_ns 0x444C (10G)
0x446C (1G)