Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683026
Date 12/14/2023

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Document Table of Contents Procedure1. Procedure1. Procedure1. Procedure

You can compile and simulate the design by running a simulation script from the command prompt.
  1. At the command prompt, change the working directory to <Example Design>\simulation\ed_sim\<Simulator> .
  2. If you change the target device in the hardware design example and regenerate the IP component (refer to the Changing Target Device in Hardware Design Example section), perform the steps in the Updating PHY IP Design File Names section. Otherwise, skip this step.
  3. Run the simulation script for the simulator of your choice.
  4. Simulator Working Directory Command
    ModelSim* <Example Design>/simulation/ed_sim/mentor vsim -c -do tb_run.tcl
    VCS* <Example Design>/simulation/ed_sim/synopsys/vcs sh tb_run.sh
    Xcelium* <Example Design>/simulation/ed_sim/xcelium sh tb_run.sh
    Note: Only VCS simulator is supported for the design example with IEEE 1588v2 feature.
A successful simulation ends with the following message:
Simulation passed.
After successful completion, you can analyze the results.