Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683026
Date 12/14/2023
Public

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Document Table of Contents

8.1. Register Access Definition

Table 27.  Types of Register Access
Access Definition
RO Read only.
RW Read and write.
RWC Read, and write and clear. The user application writes 1 to the register bit(s) to invoke a defined instruction. The IP clears the bit(s) upon executing the instruction.