Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide
ID
683026
Date
12/14/2023
Public
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1. Quick Start Guide
2. 10GBASE-R Ethernet Design Example
3. 10M/100M/1G/2.5G/10G Ethernet Design Example
4. 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature
5. 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature
6. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
7. Interface Signals Description
8. Configuration Registers Description
9. Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
10. Document Revision History for the Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide
2.3.1. Design Components
Component | Description | |
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LL 10GbE MAC | The Low Latency Ethernet 10G MAC Intel® FPGA IP with the following configuration:
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PHY |
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Transceiver Reset Controller | The Transceiver PHY Reset Controller Intel® Stratix® 10 FPGA IP. Resets the transceiver. | |
Address decoder | Decodes the addresses of the components. | |
Reset synchronizer | Synchronizes the reset of all design components. | |
ATX PLL | Generates a TX serial clock for the Intel® Stratix® 10 10G transceiver. |
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FIFO |
By default, the maximum packet length is supported up to 8000 bytes. You can configure the FIFO depth to increase the packet length. Refer to Configuring FIFO Depth for Streaming Loopback for steps to configure the FIFO depth. |
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Core fPLL | Generates 312.5 MHz and 156.25 MHz clocks to the MAC IP, reset synchronizer, Ethernet traffic controller, address decoder, and FIFO. |