Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683026
Date 12/14/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

7.1. Clock and Reset Interface Signals

Table 19.  Clock and Reset Interface Signals
Signal Direction Width Description
csr_clk In 1 125 MHz configuration clock for the Avalon® memory-mapped interface and core logic. In Intel® Stratix® 10 devices, it also provides clock for core logics.
csr_rst_n In 1 Active-low reset signal for the Avalon® memory-mapped interface.
tx_rst_n In 1 Active-low reset signal for the TX datapath.
rx_rst_n In 1 Active-low reset signal for the RX datapath.
mac_clk In 1 156.25 MHz configuration clock for the Avalon® streaming interface and 0 ppm frequency difference with refclk.
refclk In 1 125 MHz reference clock for the TX PLLs .
ref_clk_clk In 1 644.53125 MHz clock for the TX PLL.
core_clk_312 Out 1 312.5 MHz clock for the fast domain.
core_clk_156 Out 1 156.25 MHz clock for the slow domain.
rx_pma_clkout Out 1 CDR recovered clock.
reset In 1 Assert this asynchronous and active-high signal to reset the whole design example.
tx_digitalreset In [NUM_CHANNELS] Asynchronous and active-high signal to reset PCS TX portion of the transceiver PHY.
rx_digitalreset In [NUM_CHANNELS] Asynchronous and active-high signal to reset PCS RX portion of the transceiver PHY.
tx_digitalreset_stat Out [NUM_CHANNELS] Status signal for tx_digitalreset from PHY.
rx_digitalreset_stat Out [NUM_CHANNELS] Status signal for rx_digitalreset from PHY.
tx_analogreset In [NUM_CHANNELS] Asynchronous and active-high signal to reset PMA TX portion of the transceiver PHY
rx_analogreset In [NUM_CHANNELS] Asynchronous and active-high signal to reset PMA RX portion of the transceiver PHY.
tx_analogreset_stat Out [NUM_CHANNELS] Status signal for tx_analogreset from PHY.
rx_analogreset_stat Out [NUM_CHANNELS] Status signal for rx_analogreset from PHY.