Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide

Download PDF
ID 683026
Date 12/14/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. 10GBASE-R Ethernet Design Example 3. 10M/100M/1G/2.5G/10G Ethernet Design Example 4. 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature 5. 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature 6. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example 7. Interface Signals Description 8. Configuration Registers Description 9. Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 10. Document Revision History for the Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design 1.3. Compiling and Simulating the Design 1.4. Changing Target Device in Hardware Design Example 1.5. Compiling and Testing the Design in Hardware
1.2. Generating the Design x
1.2.1. Procedure 1.2.2. Design Example Parameters
1.3. Compiling and Simulating the Design x
1.3.1. Procedure 1.3.2. Testbench
1.3.1. Procedure x
1.3.1.1. Updating PHY IP Design File Names
1.4. Changing Target Device in Hardware Design Example x
1.4.1. Procedure
1.5. Compiling and Testing the Design in Hardware x
1.5.1. Procedure 1.5.2. Hardware Setup
2. 10GBASE-R Ethernet Design Example x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Interface Signals 2.7. Configuration Registers
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clocking and Reset Scheme
2.5. Hardware Testing x
2.5.1. Test Cases 2.5.2. Configuring FIFO Depth for Avalon® Streaming Loopback 2.5.3. Running Avalon® Streaming Loopback Test Case with Jumbo Ethernet Packets
3. 10M/100M/1G/2.5G/10G Ethernet Design Example x
3.1. Features 3.2. Hardware and Software Requirements 3.3. Functional Description 3.4. Simulation 3.5. Hardware Testing 3.6. Interface Signals 3.7. Configuration Registers
3.3. Functional Description x
3.3.1. Design Components 3.3.2. Clocking Scheme 3.3.3. Reset Scheme 3.3.4. Timing Constraints
3.5. Hardware Testing x
3.5.1. Test Procedure
4. 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature x
4.1. Features 4.2. Hardware and Software Requirements 4.3. Functional Description 4.4. Simulation 4.5. Hardware Testing 4.6. Interface Signals 4.7. Configuration Registers
4.3. Functional Description x
4.3.1. Design Components 4.3.2. Clocking Scheme 4.3.3. Reset Scheme 4.3.4. Timing Constraints
4.4. Simulation x
4.4.1. Test Case—Design Example with the IEEE 1588v2 Feature
4.5. Hardware Testing x
4.5.1. Test Procedure
5. 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature x
5.1. Features 5.2. Hardware and Software Requirements 5.3. Functional Description 5.4. Simulation 5.5. Hardware Testing 5.6. Interface Signals 5.7. Configuration Registers
5.3. Functional Description x
5.3.1. Design Components 5.3.2. Clocking Scheme 5.3.3. Reset Scheme 5.3.4. Timing Constraints
5.4. Simulation x
5.4.1. Test Case—Design Example with the IEEE 1588v2 Feature
5.5. Hardware Testing x
5.5.1. Changing to SFP+ Setting 5.5.2. Test Procedure
6. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example x
6.1. Features 6.2. Hardware and Software Requirements 6.3. Functional Description 6.4. Simulation 6.5. Hardware Testing 6.6. Interface Signals 6.7. Configuration Registers
6.3. Functional Description x
6.3.1. Design Components 6.3.2. Clocking Scheme 6.3.3. Reset Scheme
6.4. Simulation x
6.4.1. Test Case—Design Example with the IEEE 1588v2 Feature 6.4.2. Test Case—Design Example without the IEEE 1588v2 Feature
6.5. Hardware Testing x
6.5.1. Test Procedure
7. Interface Signals Description x
7.1. Clock and Reset Interface Signals 7.2. Avalon® Memory-Mapped Interface Signals 7.3. Avalon® Streaming Interface Signals 7.4. PHY Interface Signals 7.5. Status Interface 7.6. IEEE 1588v2 Timestamp Interface Signals 7.7. Packet Classifier Interface Signals 7.8. TOD Interface Signals
8. Configuration Registers Description x
8.1. Register Access Definition 8.2. Low Latency Ethernet 10G MAC 8.3. PHY 8.4. Transceiver Reconfiguration 8.5. TOD
8.3. PHY x
8.3.1. 1G/2.5G/5G/10G Multi-rate PHY
1. Quick Start Guide
2. 10GBASE-R Ethernet Design Example
3. 10M/100M/1G/2.5G/10G Ethernet Design Example
4. 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature
5. 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature
6. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
7. Interface Signals Description
8. Configuration Registers Description
9. Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
10. Document Revision History for the Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide

7.2. Avalon® Memory-Mapped Interface Signals

Table 20.   Avalon® Memory-Mapped Interface Signals
Signal Direction Description

write

csr_mac_write

csr_phy_write

csr_rcfg_write

csr_native_phy_rcfg_write

csr_master_tod_write

csr_mch_write

In Assert this signal to request a write.

read

csr_mac_read

csr_phy_read

csr_rcfg_read

csr_native_phy_rcfg_read

csr_master_tod_read

csr_mch_read

In Assert this signal to request a read.

address

csr_mac_address

csr_phy_address

csr_rcfg_address

csr_native_phy_rcfg_address

csr_master_tod_address

csr_mch_address 		In Use this bus to specify the register address you want to read from or write to.

writedata

csr_mac_writedata

csr_phy_writedata

csr_rcfg_writedata

csr_native_phy_rcfg_writedata

csr_master_tod_writedata

csr_mch_writedata

In Carries the data to be written to the specified register.

readdata

csr_mac_readdata

csr_phy_readdata

csr_rcfg_readdata

csr_native_phy_rcfg_readdata

csr_master_tod_readdata

csr_mch_readdata

Out Carries the data read from the specified register.

waitrequest

csr_mac_waitrequest

csr_phy_waitrequest

csr_native_phy_rcfg_waitrequest

csr_master_tod_waitrequest

csr_mch_waitrequest

Out When asserted, this signal indicates that the IP is busy and not ready to accept any read or write requests.
Level Two Title