Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683026
Date 12/14/2023

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6.5. Hardware Testing

Follow the procedure at the provided link to test the design example in the selected hardware.

In the Clock Controller application, which is part of the development kit, set the following frequencies :

  • U5, Out 5—644.53125MHz
  • U5, Out0—125 MHz
    Note: This is only applicable when you generate the design example with IEEE 1588v2 feature.
  • U6, Out 8—125MHz