Intel® High Level Synthesis Accelerator Functional Unit Design Example User Guide

ID 683025
Date 7/19/2019
Document Table of Contents

4. HLS AFU Design Example Description

The HLS AFU design comprises an AFU (contained in the hw folder) that runs on an Intel® FPGA Programmable Acceleration Card (Intel® FPGA PAC), and a host application that runs on an Intel® Xeon® CPU.