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2.1. HLS AFU Design Example Software Requirements
2.2. Compiling and Simulating the HLS Component with the i++ Command
2.3. Generating a Platform Designer Container for the HLS Component
2.4. Generating the ASE Testbench
2.5. Running the ASE Testbench
2.6. Compiling the AF Bitstream
2.7. Loading AF Bitstream and Running the Host Application
5.1. Platform Designer Opens with an Error
5.2. The design unit was not found Error When Running the make sim Command
5.3. Verilog HDL Compilation Errors
5.4. Compilation Errors During ASE Testbench Generation
5.5. Incorrect Output During Simulation
5.6. AF Bitstream Compilation Fails
5.7. Verilog Files Not Found Errors
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5.6. AF Bitstream Compilation Fails
Make sure that you don't have any unused IPs defined in filelist.txt. Delete the Platform Designer-generated files (hls_afu_container directory) from the hls_afu/hw/rtl/qsys directory