Intel® High Level Synthesis Accelerator Functional Unit Design Example User Guide

ID 683025
Date 7/19/2019
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2.2. Compiling and Simulating the HLS Component with the i++ Command

As with other HLS design examples, you can compile this example design using the included makefile. This makefile uses similar conventions to the HLS design examples.
Ensure your development environment includes the Intel® HLS Compiler Pro Edition Version 19.1 or later.
Note: The HLS code might not compile if you are using the Intel® HLS Compiler Pro Edition Version 19.1 in an environment that does not have the correct version of the GCC libraries. To ensure that you have the correct libraries, review the instructions in the Intel High Level Synthesis Compiler Getting Started Guide.
  1. Initialize your current session so that you can run the Intel® HLS Compiler. In your terminal session, change directories to the hls directory in your Acceleration Stack installation directory.
    For example:
    $ cd /home/<username>/inteldevstack/intelFPGA_pro/hls
  2. Run the following command from the hls directory to set the environment variables for the i++ command in the current terminal session:
    $ source init_hls.sh
    The environment initialization script shows the environment variables that it sets.
  3. Navigate to the HLS soruce code.
    The HLS source code is in <design location>/hls_afu/hw/rtl/hls/.
  4. Build and emulate the design using x86 instructions run these commands:
    $ make test-x86-64
    $ ./test-x86-64
    The test-x86-64 command gives you the following output:
    i++ src/hls_afu.cpp src/test.cpp   --fp-relaxed -ghdl  -march=x86-64 -o test-x86-64
    +--------------------------------------------+
    | Run ./test-x86-64 <n> to execute the test. |
    | <n> is 0, 1, or 2 depending on desired     |
    | test behavior:                             |
    |         <n> | effect                       |
    |       ------+--------------------          |
    |          0  | test both (default)          |
    |          1  | test ac_int only             |
    |          2  | test float only              |
    +--------------------------------------------+
    Control which component gets tested by passing an integer!
    arg   | effect
    ------+--------------------
       0  | test both (default)
       1  | test ac_int only
       2  | test float only
    test AC_INT version and FLOAT version
    
    AC_INT COMPONENT - 81 ELEMENTS
    ac_inc:
    sizeof(uint512) = 64 (64)
    number of 512 bit (64-byte) numbers: 6
    PASS
    
    FLOATING-POINT COMPONENT - 81 ELEMENTS
    fp_inc:
    PASS
    OVERALL:
    PASSED
    
  5. Generate RTL and simulate generated RTL with the ModelSim simulator:
    $ make test-fpga
    $ ./test-fpga
    The test-fpga command gives you the following output:
    Control which component gets tested by passing an integer!
    arg   | effect              
    ------+-------------------- 
       0  | test both (default) 
       1  | test ac_int only    
       2  | test float only     
    test AC_INT version and FLOAT version
    
    AC_INT COMPONENT - 81 ELEMENTS
    ac_inc:
    sizeof(uint512) = 64 (64)
    number of 512 bit (64-byte) numbers: 6
    PASS
    
    FLOATING-POINT COMPONENT - 81 ELEMENTS
    fp_inc:
    PASS
    OVERALL:
    PASSED
  6. Confirm that the outputs from the test-x86-64 command and the test-fpga command match.

    The test-x86-64 command runs C++ code on the processor, while the test-fpga command compiles the C++ source to to Verilog RTL and then simulates the generate RTL using the testbench defined in the code.

    For instructions about how to view the waveforms for this component, see the Intel High Level Synthesis Compiler User Guide.