Intel® High Level Synthesis Accelerator Functional Unit Design Example User Guide

ID 683025
Date 7/19/2019
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Document Table of Contents
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2.1. HLS AFU Design Example Software Requirements

Ensure that you configure your system for building Intel Acceleration Stack designs as described in the Intel Acceleration Stack Quick Start Guide for Intel Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

Before you use the design example, install the following software:

  • Intel Acceleration Stack for Development Version 1.2 or later (and associated prerequisites)

    The Acceleration Stack includes Intel® Quartus® Prime Pro Edition Version 17.1.1

  • Intel® High Level Synthesis (HLS) Compiler Version 19.1 or later to compile your HLS code

    Get the Intel® High Level Synthesis Compiler from the Additional Software tab of the Intel® Quartus® Prime Pro Edition Version 19.1 download page at the Download Center for FPGAs.

    For instructions about how to integrate Intel® HLS Compiler Pro Edition Version 19.1 into your Intel® Quartus® Prime Pro Edition Version 17.1.1 installation, review the Intel High Level Synthesis Compiler Getting Started Guide.

  • (Optional) 64-bit Mentor ModelSim* SE* Simulator (Version 10.5c) or 64-bit Mentor Questa* Advanced Simulator (Version 10.5c)

    These simulators are required if you want to simulate the AFU.

    If you want to simulate only the HLS component, you can use the 32-bit ModelSim* - Intel® FPGA Edition software.