Intel® High Level Synthesis Accelerator Functional Unit Design Example User Guide

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ID 683025
Date 7/19/2019
Public
Document Table of Contents
Document Table of Contents x
1. About the HLS AFU Design Example 2. Building the HLS AFU Design Example 3. Customizing the HLS AFU 4. HLS AFU Design Example Description 5. Troubleshooting HLS AFU Designs 6. Document Revision History for the HLS AFU Design Example User Guide
1. About the HLS AFU Design Example x
1.1. HLS AFU Design Example Files 1.2. Acronyms in the HLS AFU Design Example User Guide
2. Building the HLS AFU Design Example x
2.1. HLS AFU Design Example Software Requirements 2.2. Compiling and Simulating the HLS Component with the i++ Command 2.3. Generating a Platform Designer Container for the HLS Component 2.4. Generating the ASE Testbench 2.5. Running the ASE Testbench 2.6. Compiling the AF Bitstream 2.7. Loading AF Bitstream and Running the Host Application
3. Customizing the HLS AFU x
3.1. Acceleration Stack Configuration Files
4. HLS AFU Design Example Description x
4.1. AFU Description 4.2. Host Application Description
4.1. AFU Description x
4.1.1. HLS AFU Container
4.1.1. HLS AFU Container x
4.1.1.1. HLS AFU Avalon-MM I/O Slave Interface 4.1.1.2. HLS AFU Avalon-MM Master Interfaces
5. Troubleshooting HLS AFU Designs x
5.1. Platform Designer Opens with an Error 5.2. The design unit was not found Error When Running the make sim Command 5.3. Verilog HDL Compilation Errors 5.4. Compilation Errors During ASE Testbench Generation 5.5. Incorrect Output During Simulation 5.6. AF Bitstream Compilation Fails 5.7. Verilog Files Not Found Errors
1. About the HLS AFU Design Example
2. Building the HLS AFU Design Example
3. Customizing the HLS AFU
4. HLS AFU Design Example Description
5. Troubleshooting HLS AFU Designs
6. Document Revision History for the HLS AFU Design Example User Guide

2. Building the HLS AFU Design Example

You need to run various commands to build and test the HLS AFU design. If you want to quickly verify your set-up, you can follow the abbreviated instructions in the example design /hls_afu/README.txt file.

The design example shows how you add an Intel® HLS Compiler component to an Acceleration Stack AFU. The HLS AFU design example targets the Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA. It includes:

  • An AFU that runs on an FPGA. You can compile the platform-agnostic AFU into a platform-specific accelerator function (AF) that executes on the FPGA. This function interacts with memory on the host computer (host memory) through the core cache interface (CCI-P).
  • Host software that runs on an Intel Xeon CPU. This software provides your application logic and is responsible for allocating memory to be shared with the AF, sending data to the FPGA, and collecting the results when the AF finishes executing.
Building the design examples includes the following steps:
  1. Compile and simulate the HLS component with the Intel® HLS Compiler to verify functional correctness.
  2. Add the HLS component to an AFU by creating a Platform Designer container.
  3. Cosimulate the design with the Intel AFU Simulation Environment (ASE) to confirm the AFU functionality after adding the HLS component:
    1. Generate the ASE testbench.
    2. Run the ASE testbench.
  4. Compile the AF bitstream.
  5. Load the AF bitstream on hardware and run the host application.

Section Content
HLS AFU Design Example Software Requirements
Compiling and Simulating the HLS Component with the i++ Command
Generating a Platform Designer Container for the HLS Component
Generating the ASE Testbench
Running the ASE Testbench
Compiling the AF Bitstream
Loading AF Bitstream and Running the Host Application

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