Intel® High Level Synthesis Accelerator Functional Unit Design Example User Guide

ID 683025
Date 7/19/2019
Document Table of Contents

2. Building the HLS AFU Design Example

You need to run various commands to build and test the HLS AFU design. If you want to quickly verify your set-up, you can follow the abbreviated instructions in the example design /hls_afu/README.txt file.

The design example shows how you add an Intel® HLS Compiler component to an Acceleration Stack AFU. The HLS AFU design example targets the Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA. It includes:

  • An AFU that runs on an FPGA. You can compile the platform-agnostic AFU into a platform-specific accelerator function (AF) that executes on the FPGA. This function interacts with memory on the host computer (host memory) through the core cache interface (CCI-P).
  • Host software that runs on an Intel Xeon CPU. This software provides your application logic and is responsible for allocating memory to be shared with the AF, sending data to the FPGA, and collecting the results when the AF finishes executing.