Intel® High Level Synthesis Accelerator Functional Unit Design Example User Guide

ID 683025
Date 7/19/2019
Public
Document Table of Contents

1. About the HLS AFU Design Example

The Intel High Level Synthesis (HLS) Accelerator Functional Unit (AFU) design example shows how to create AFUs for the Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs with with the Intel® HLS Compiler

Before continuing, you should be familiar with the fundamentals of both the Intel® HLS Compiler and the Acceleration Stack.

This design example transfers data between a host program and a simple AFU generated with the Intel® HLS Compiler. The AFU is a vector reduction design named hls_afu, and the design example uses ac_int and float datatypes.

To obtain the HLS AFU Design Example code, contact an Intel Sales agent.

You can use this code as a model to create your own HLS AFUs if your AFUs use the same interfaces as the example design. Also, you might be able to convert your HLS application into an AFU by adding the required interfaces to the hardware design.

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