F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 4/01/2024
Document Table of Contents

4.4.6. UI Adjustment

This section provides steps to measure UI value to prevent time drift due to clock PPM differences as referenced to golden time-of-day (TOD) in the platform.
Tip: The TOD value increments constantly based on the golden TOD running at the ideal clock with 0 ppm difference. If you observe a large adjustment to the TOD value, don't perform measurement or discard any performed measurement as it impacts the measurement result.

TAM is the reference time for Alignment Marker (AM) for variants with AM, and an arbitrary selected reference bit for variants without AM.

For simulation or hardware run with 0 ppm setting, you can skip the measurement and program 0 ppm UI value as defined in the table.
Table 19.  Default or 0 ppm UI Value
Attention: The UI value provided in this table is different from the UI value at serial line in the UI Value and PMA Delay section.
Mode 0 ppm UI value (ps) 0 ppm UI value

{4-bit ns, 28-bit fractional ns}

10GE-1 96.9697 32’h018D3019
25GE-1 38.7878 32’h 009EE00A
50GE-1 19.3939 32’h004F7005
100GE-1 9.6969 32’h0027B802