F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 6/05/2024
Document Table of Contents

1.2. F-Tile Ethernet Intel® FPGA Hard IP Overview

The F-Tile Ethernet Intel® FPGA Hard IP core consists of synthesizable soft-logic and the hardened IP core block. Each F-Tile Ethernet Intel® FPGA Hard IP core consists of a single Ethernet port, configurable for 10GE, 25GE, 40GE, 50GE, 100GE, 200GE, or 400GE data rate.

The F-Tile Ethernet Intel® FPGA Hard IP does not support multiport configuration. You can enable multiport configuration by instantiating multiple IP instances.

The figure below displays the IP core block diagram, showing significant blocks and connections. The same implementation applies to all supported data rate IP options.

Figure 2.  F-Tile Ethernet Intel® FPGA Hard IP Block Diagram

The TX/RX MAC Adapters provide an optional MAC Avalon ST interface for 10GE/25GE/40GE/50GE/100GE ports, which can also provide an asynchronous interface, and converts from multiple segments to a wide MAC Avalon ST datapath. The MAC Avalon ST client interface is not available for 200GE and 400GE ports.

The F-tile is connected to the FPGA fabric using Intel's embedded multi-die interconnect bridge (EMIB) technology. The EMIB Deskew block corrects for possible skew over the EMIB interfaces between the main FPGA die and the F-Tile. Typically, the 40GE/50GE/100GE/200GE/400GE ports access the EMIB Deskew block. The 10GE/25GE ports that use PTP can also access this block.

The TX/RX Data Path (DP) mapping functions map the Ethernet IP signals to the EMIB datapath.

The PTP soft component logic block enables the PTP interface. The block performs the soft logic operations required for the F-Tile timestamp system for 1588 PTP support and connects to the time-of-day (TOD) module.

The PCS interface and the PCS66 interface follows the path through the EMIB Deskew and DP Mapping stages. The interface does not use adapters.

The Auto-negotiation and Link Training (AN/LT) port connects to a separate F-Tile Auto-Negotiation and Link Training for Ethernet Intel® FPGA IP. When enabled, the IP provides the status and control information.

The Reconfiguration and reset logic implement the reconfiguration interfaces and resets for the core, respectively.

Avalon® memory-mapped interface (Avalon MM) Adapters communicate with the F-tile raw Avalon® memory-mapped interface, allowing an 8-to-32 bit conversion on the transactions.

Optional Debug Master Endpoints instantiate the Avalon MM interfaces via GUI options to enable Transceiver Toolkit and Ethernet Toolkit software utilities. This feature is planned for future release.

32-bit soft CWBIN counters are implemented in Soft IP and this parameter can be enabled for all FEC modes. This soft logic converts the 8-bit CWBin0-3 register (FEC block of F-Tile) of the Hard IP to 32-bit soft logic registers.