F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 4/01/2024
Document Table of Contents

7.13. Reconfiguration Interfaces

Both Ethernet reconfiguration interfaces and Transceiver reconfiguration interfaces have a readdata_valid port, which makes them compatible with pipelined read bus master. Enabling it has no effect on the throughput.

For more information, refer to the Pipelined Transfers of Avalon Interface Specifications section.