F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 4/01/2024
Document Table of Contents

4.3.2. OTN Mode

The F-Tile Ethernet Intel® FPGA Hard IP supports OTN mode in all Ethernet modes with optional RS-FEC feature.

The TX OTN datapath consists of:
  • Alignment insertion—Alignment Marker and its position are made available for OTN based on the Ethernet mode of operation. Refer to Signals of the PCS66 TX Interface table for more information.
  • Striper—enables logically sequential data to be segmented to increase data throughput.
Note: In OTN mode in 10GE/20GE/40GE/50GE/100GE Ethernet modes, scrambler is bypassed because the input data is expected to be scrambled. In 200GE/400GE Ethernet modes, RS-FEC block descrambles the data.

The RX OTN datapath consists of an aligner block that enables the alignment of the incoming data.