F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 4/01/2024
Document Table of Contents

7.13.2. Transceiver Reconfiguration Interfaces

You access the control and status registers of the Agilex™ 7 F-tile transceivers during normal operation using an Avalon® memory-mapped interface. The interface responds regardless of the link status. It also responds when the IP core is in a reset state driven by any reset signal or soft reset other than the i_reconfig_reset signal.

Asserting the i_reconfig_reset signal resets all transceiver reconfiguration control and status registers, including the statistics counters; while this reset is in process, reads and writes to addresses in the F-Tile Ethernet Intel® FPGA Hard IP is delayed.

Table 57.  Transceiver Reconfiguration Interface Ports to Native PHY Reconfiguration InterfacesThe signals in this interface are clocked by the i_reconfig_clk clock and reset by the i_reconfig_reset signal. The signal names are standard Avalon® memory-mapped interface signals.
  • n = index of transceiver associated with the reconfiguration interface, from 0 to (number of lanes - 1)
Port Name Width Description


18 bits

Address bus for transceiver control and status registers.


1 bit

Transceiver read signal.

When asserted, starts a read cycle.


1 bit

Transceiver write signal.

When asserted, writes data on the reconfiguration write data bus.


4 bits

Transceiver byte enable signal for read and write request.


32 bits

Transceiver read data bus.

When asserted, presents transceiver data read on a read cycle.


1 bit

Read data from Transceiver read data bus is valid.


32 bits

Transceiver write data bus.

When asserted, presents transceiver data written on a write cycle.


1 bit Indicates the Avalon® memory-mapped interface is busy. The read or write cycle is only complete when this signal goes low.