F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 4/01/2024
Document Table of Contents

9.2.1. Overview

PTP tile adapter transfers the PTP signals between the Ethernet IP and the tile.

The PTP tile adapter module is generated along with the Ethernet IP when you enable PTP option in the Ethernet IP parameter editor. In your design, you must instantiate PTP tile adapter (eth_ptp_adpt_f) instance and connect it to the F-Tile Ethernet Intel® FPGA Hard IP. A single PTP tile adapter instance accommodates all PTP variants on the same F-tile.

The module transfers the signals through dedicated EMIB6 and EMIB7 channels. While connection between adapter and tile is automatic, you must manually connect the bus interface between the PTP tile adapter and the associated F-Tile Ethernet Intel® FPGA Hard IP. You access the EMIB6 and EMIB7 registers for Asymmetry Delay and P2P Mean Path Delay through the Avalon® memory-mapped interface. To align data transfer across multiple EMIBs from the FPGA fabric to the tile, the PTP Tile Adapter also generates TX deskew pulse for EMIBs of the Ethernet IP with PTP enabled.