F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 6/05/2024
Document Table of Contents

4.4. Precision Time Protocol

The Precision Time Protocol (PTP) provides 1588 Precision Time Protocol timestamp information as defined in the IEEE 1588-2008 Precision Clock Synchronization Protocol for Networked Measurement and Control System Standard. 1588 PTP logic generates 96-bit timestamp information for transmitted and received packets. The generated timestamps represent the time when the first bit after the Start of Frame Delimiter (SFD) byte crosses the FPGA serial pins (Medium Dependent Interface, MDI).

In a 1-step TX operation, the IP core updates the PTP message content on-the-fly during the packet transmission. The update includes a 96-bit 1588 v2 format timestamp, updated correction field with residence time, asymmetry delay, and the peer-to-peer mean path delay. The IP core sets the UDP/IPv4 checksum field to zero and updates extended bytes to a correct checksum of the UDP/IPv6 packets.

A fingerprint can accompany a 1588 PTP packet. You can use this information to associate returned TX timestamp to the transmitted PTP packet. If you provide fingerprint information, the IP core passes it through unchanged.

The IP core connects to a time-of-day (TOD) module that continuously provides the current time of day based on the input clock frequency.

Once PTP is enabled, you must instantiate PTP tile adapter module (eth_ptp_adpt_f) per each F-tile. A single PTP tile adapter instance accommodates all PTP variants on the same F-tile. You must manually connect the bus interface between the PTP tile adapter and the associated F-Tile Ethernet Intel® FPGA Hard IP For more information about the PTP tile adapter, refer to PTP Tile Adapter.
Note: The PTP tile adapter requires dedicated use of EMIB 6 and EMIB 7 channels.

For proper connectivity between the F-Tile Ethernet Intel® FPGA Hard IP in PTP mode and the supporting logic blocks, refer to the F-Tile Ethernet Intel® FPGA Hard IP Design Example.