F-Tile Ethernet Intel® FPGA Hard IP User Guide

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ID 683023
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. F-Tile Ethernet Intel® FPGA Hard IP Parameters 4. Functional Description 5. Clocks 6. Resets 7. Interface Overview 8. Configuration Registers 9. Supported Modules and IPs 10. Supported Tools 11. F-Tile Ethernet Intel® FPGA Hard IP User Guide Archives 12. Document Revision History for the F-Tile Ethernet Intel® FPGA Hard IP User Guide
1. Overview x
1.1. Ethernet System in F-Tile Overview 1.2. F-Tile Ethernet Intel® FPGA Hard IP Overview
1.2. F-Tile Ethernet Intel® FPGA Hard IP Overview x
1.2.1. Device Family Support 1.2.2. Device Speed Grade Support 1.2.3. Resource Utilization 1.2.4. Round-trip Latency 1.2.5. Release Information
2. Getting Started x
2.1. Installing and Licensing F-Tile Ethernet Intel® FPGA Hard IP Cores 2.2. Specifying the IP Core Parameters and Options 2.3. Reference and System PLL Clock for your IP Design 2.4. Generated File Structure 2.5. Generating Tile Files 2.6. IP Core Testbenches
2.4. Generated File Structure x
2.4.1. Generating IP-XACT File
4. Functional Description x
4.1. Datapath Description 4.2. F-Tile Ethernet Intel® FPGA Hard IP MAC 4.3. PCS, OTN, and FlexE Modes 4.4. Precision Time Protocol 4.5. Auto-Negotiation and Link Training
4.2. F-Tile Ethernet Intel® FPGA Hard IP MAC x
4.2.1. MAC TX Datapath 4.2.2. MAC RX Datapath 4.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) 4.2.4. Link Fault Signaling 4.2.5. Order of Ethernet Transmission
4.2.1. MAC TX Datapath x
4.2.1.1. TX Preamble, Start, and SFD Insertion 4.2.1.2. Source Address Insertion 4.2.1.3. Length/Type Field Processing 4.2.1.4. Frame Padding 4.2.1.5. Frame Check Sequence (CRC-32) Insertion 4.2.1.6. Inter-Packet Gap Generation and Insertion 4.2.1.7. TX Packing Logic
4.2.2. MAC RX Datapath x
4.2.2.1. RX Preamble Processing 4.2.2.2. RX Strict SFD Checking 4.2.2.3. RX FCS Checking 4.2.2.4. RX Malformed Packet Handling 4.2.2.5. Removing PAD Bytes and FCS Bytes from RX Frames 4.2.2.6. RX Undersized Frames, Oversized Frames, and Frames with Length Errors 4.2.2.7. Inter-Packet Gap
4.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) x
4.2.3.1. Conditions Triggering XOFF Frame Transmission 4.2.3.2. Conditions Triggering XON Frame Transmission 4.2.3.3. Pause Control and Generation Interface 4.2.3.4. Pause Control Frame Filtering
4.3. PCS, OTN, and FlexE Modes x
4.3.1. PCS Mode 4.3.2. OTN Mode 4.3.3. FlexE Mode
4.4. Precision Time Protocol x
4.4.1. Features 4.4.2. PTP Timestamp Accuracy 4.4.3. PTP Client Flow 4.4.4. RX Virtual Lane Offset Calculation for No FEC Variants 4.4.5. Virtual Lane Order and Offset Values 4.4.6. UI Adjustment 4.4.7. Reference Time Interval 4.4.8. Minimum and Maximum Reference Time (TAM) Interval for UI Measurement (Hardware) 4.4.9. UI Value and PMA Delay 4.4.10. Routing Delay Adjustment for Advanced Timestamp Accuracy Mode 4.4.11. Routing Delay Adjustment for Basic Timestamp Accuracy Mode
4.4.3. PTP Client Flow x
4.4.3.1. PTP TX Client Flow 4.4.3.2. PTP RX Client Flow
4.4.6. UI Adjustment x
4.4.6.1. TX UI Adjustment 4.4.6.2. RX UI Adjustment
5. Clocks x
5.1. Clock Connections in Single Instance Operation 5.2. Clock Connections in Multiple Instance Operation 5.3. Clock Connections in MAC Asynchronous FIFO Operation 5.4. Clock Connections in PTP-Based Synchronous and Asynchronous Operation 5.5. Clock Connections in Synchronous Ethernet Operation 5.6. Custom Cadence
6. Resets x
6.1. Reset Signals 6.2. Reset Sequence
7. Interface Overview x
7.1. Status Interface 7.2. TX MAC Avalon ST Client Interface 7.3. RX MAC Avalon ST Aligned Client Interface 7.4. TX MAC Segmented Client Interface 7.5. RX MAC Segmented Client Interface 7.6. MAC Flow Control Interface 7.7. PCS Mode TX Interface 7.8. PCS Mode RX Interface 7.9. FlexE and OTN Mode TX Interface 7.10. FlexE and OTN Mode RX Interface 7.11. Custom Rate Interface 7.12. 32-bit Soft CWBIN Counters 7.13. Reconfiguration Interfaces 7.14. Precision Time Protocol Interface
7.2. TX MAC Avalon ST Client Interface x
7.2.1. TX MAC Avalon ST Client Interface with Disabled Preamble Passthrough 7.2.2. TX MAC Avalon ST Client Interface with Enabled Preamble Passthrough 7.2.3. Using MAC Avalon ST skip_crc Signal to Control Source Address, PAD, and CRC Insertion 7.2.4. Using MAC Avalon ST i_tx_error Signal to Mark Packets Invalid
7.3. RX MAC Avalon ST Aligned Client Interface x
7.3.1. RX MAC Avalon ST Client Interface with Disabled Preamble Passthrough 7.3.2. RX MAC Avalon ST Client Interface with Enabled Passthrough and RX CRC Forwarding 7.3.3. RX MAC Adapter Limitations 7.3.4. RX MAC Avalon ST Client Interface Status
7.4. TX MAC Segmented Client Interface x
7.4.1. TX MAC Segmented Client Interface with Disabled Preamble Passthrough 7.4.2. TX MAC Segmented Client Interface with Enabled Preamble Passthrough 7.4.3. Using MAC Segmented skip_crc Signal to Control Source Address, PAD, and CRC Insertion 7.4.4. Using MAC Segmented i_tx_mac_error to Mark Packets Invalid
7.5. RX MAC Segmented Client Interface x
7.5.1. RX MAC Segmented Client Interface with Disabled Preamble Passthrough 7.5.2. RX MAC Segmented Client Interface with Enabled Passthrough and RX CRC Forwarding 7.5.3. RX MAC Segmented Client Interface Status and Errors
7.13. Reconfiguration Interfaces x
7.13.1. Ethernet Reconfiguration Interfaces 7.13.2. Transceiver Reconfiguration Interfaces
7.14. Precision Time Protocol Interface x
7.14.1. Time-of-Day Interface 7.14.2. TX 2-Step Timestamp Interface 7.14.3. TX 1-Step Timestamp Interface 7.14.4. RX Timestamp Interface 7.14.5. PTP Status Interface 7.14.6. PTP Tile Interface
7.14.3. TX 1-Step Timestamp Interface x
7.14.3.1. PTP Field Offset for 1-Step Operation
8. Configuration Registers x
8.1. Ethernet Avalon® Memory-Mapped Interface Address Space 8.2. Transceiver Avalon® Memory-Mapped Interface Address Space
8.1. Ethernet Avalon® Memory-Mapped Interface Address Space x
8.1.1. Ethernet Hard IP Core CSRs 8.1.2. FEC and Transceiver Control and Status Registers
9. Supported Modules and IPs x
9.1. F-Tile Auto-Negotiation and Link Training For Ethernet Intel® FPGA IP 9.2. PTP Tile Adapter
9.1. F-Tile Auto-Negotiation and Link Training For Ethernet Intel® FPGA IP x
9.1.1. Overview 9.1.2. Release Information 9.1.3. Functional Description 9.1.4. Parameters 9.1.5. Clocks and Resets 9.1.6. Registers
9.2. PTP Tile Adapter x
9.2.1. Overview 9.2.2. Clocks, Reset, and Interface Ports 9.2.3. PTP Asymmetry Delay Reconfiguration Interface 9.2.4. PTP Peer-to-Peer MeanPathDelay Reconfiguration Interface
10. Supported Tools x
10.1. F-Tile Channel Placement Tool 10.2. Ethernet Toolkit Overview
10.2. Ethernet Toolkit Overview x
10.2.1. Features
1. Overview
2. Getting Started
3. F-Tile Ethernet Intel® FPGA Hard IP Parameters
4. Functional Description
5. Clocks
6. Resets
7. Interface Overview
8. Configuration Registers
9. Supported Modules and IPs
10. Supported Tools
11. F-Tile Ethernet Intel® FPGA Hard IP User Guide Archives
12. Document Revision History for the F-Tile Ethernet Intel® FPGA Hard IP User Guide

9.1.4. Parameters

The F-Tile Auto-Negotiation and Link Training for Ethernet Intel® FPGA IP parameter editor provides the parameters you can set to configure your IP variation.

The F-Tile Auto-Negotiation and Link Training for Ethernet Intel® FPGA IP parameter has the following tabs:
  • AN/LT Options
  • AN Channel Map
  • Target Profile Settings
Figure 64.  F-Tile Auto-Negotiation and Link Training for Ethernet Intel® FPGA IP Parameters: IP Tab
Note: The Target Profile Settings tab is available only when Enable Dynamic AN/LT option is selected in the AN/LT Options tab in the F-Tile Auto-Negotiation and Link Training for Ethernet Intel® FPGA IP GUI.
Table 71.   F-Tile Auto-Negotiation and Link Training for Ethernet Intel® FPGA IP Parameters: IP TabThis table does not provide information about invalid parameter value combinations. If you make selections that create a conflict, the parameter editor generates error messages in the System Messages pane.

Parameter

Range

Default Setting

Parameter Description

Mode selection
Enable auto-negotiation on reset
  • On
  • Off
 On Enable Auto-negotiation.
Enable link training on reset
  • On
  • Off
 On Enable Link Training.
Enable ECC protection
  • On
  • Off
 Off Enable Error Correction Code (ECC) for Nios® II memory.

To enable this feature, you must acquire Nios® II license. Contact Intel Sales for information about acquiring a license.

PMA type
  • FHT
  • FGT
 FGT

PMA Type.

Selects the PMA type. Each PMA has a different data rate range and compliance specifications.

The selected mode must match with PMA mode selected in Base IP.

Ethernet mode
  • 10GE-1
  • 25GE-1
  • 40GE-4
  • 50GE-2
  • 50GE-1
  • 100GE-4
  • 100GE-2
  • 100GE-1
  • 200GE-8
  • 200GE-4
  • 200GE-2
  • 400GE-8
  • 400GE-4
 10GE-1

Ethernet Configuration.

Specifies the overall port bandwidth across the number of physical lanes used by the port.

Term XGbE-Y represents:
  • X is the overall bandwidth of the port
  • Y is the number of physical lanes used by port

The selected mode must match with Ethernet mode selected in Base IP.

KR or CR mode
  • KR mode
  • CR mode
 CR mode Selects the option during auto-negotiation.
Number of ports 1-16 4 Selects number of base Ethernet IP ports connected to the IP.
FEC mode
  • None
  • IEEE 802.3 BASE-R Firecode (CL74)
  • IEEE 802.3 RS(528,514) (CL91) or

    IEEE 802.3

    RS(544,514)

    (CL134)

  • Ethernet Technology Consortium RS(272, 258)
 None

Selects the FEC mode for each port.

The IP core supports the following FEC types
  • IEEE 802.3 BASE-R Firecode (CL74) is available only for 25GE-1.

  • IEEE 802.3 RS(528,514) (CL91)

  • IEEE 802.3 RS(544,514) (CL134)

  • Ethernet Technology Consortium RS(272,258) is a low-latency substitute for RS(544,514).
Link fail inhibit time 0-20000
  • 505 (for NRZ)
  • 3150 (for 50G PAM4)
  • 12350 (for 100G PAM4)

Sets the link fail inhibit timeout for auto-negotiation in milliseconds.

Default value:
  • 505 ms for NRZ modes
  • 3150 ms for 50G PAM4 modes
  • 12350 ms for 100G PAM4 modes
Status clock frequency 100-250 100

Selects the auto-negotiation and link training status clock frequency.

Must be set to the frequency of the i_clk input for the correct timer functionality.

Enable ANLT Debug Endpoint for Ethernet Toolkit
  • On
  • Off
 Off Enables JTAG interface to external terminal so that Ethernet Tool Kit (ETK) can access the AN/LT configuration and status registers.
Enable Fast Simulation
  • On
  • Off
 On

Enable fast simulation to skip auto-negotiation and link training functionality and FHT or FGT features. Additionally, it updates the AN/LT status registers to reflect AN/LT completion.

Note: Enable Fast Simulation is not supported when Enable Dynamic AN/LT is enabled.
Enable Dynamic AN/LT
  • On
  • Off
 Off Enables the Dynamic reconfiguration feature for AN/LT IP. Make sure the correct combination of settings are used based on the base ethernet IP secondary profiles associated with the ANLT port. Selecting this parameter enables the Target Profile Settings tab.
Note: The Enable AN/LT you select depends on the base ethernet IP secondary profiles associated with the AN/LT port.

AN Channel Map

AN channel

AN channel location <n>

0-7

0
Selects the AN lane default location in each Ethernet ports. <n> is an integer from 0 to (number of lanes - 1). For example, for 100GE-4, AN channel location <n> parameter can be 0 to 3.
Note:
  • When Enable Dynamic AN/LT is set, only AN_CHAN = 0 is supported for all multi-lane designs.
  • The AN channel you select depends on the PMA physical channel connections on your board and the desired physical channel to enable AN/LT.

This option is not available for single lane (For example, 10GE-1, 25GE-1).
Target Profile Settings
Note: Make sure the correct combination of settings are used based on the base ethernet IP secondary profiles associated with the ANLT port.
Advertise Low Latency FEC Request
  • On
  • Off
 Off

Sets the value of the override consortium low-latency FEC request field, bit 3 of Register 0xCC.
Advertise RS-FEC Request
  • On
  • Off
 Off Must be set to the value of the override RS-FEC ability field, bit 10 of Register 0xCC.
Advertise RS-FEC Ability
  • On
  • Off
 Off Sets the value of the override RS-FEC ability field bit 8 of Register 0xCC.
Advertise BASER-FEC Request
  • On
  • Off
 Off Sets the value of the override BASER-FEC request field, bit 11 of Register 0xCC.
Advertise BASER-FEC Ability
  • On
  • Off
 Off Sets the value of the override BASER-FEC ability field, bit 9 of Register 0xCC.

Advertise Low Latency FEC Ability

LL FEC Ability for 50G BASE-CR1/KR1
  • On
  • Off
 Off Sets the value of the override consortium low-latency FEC ability field, bit 4 of Register 0xCC.
LL FEC Ability for 100G BASE-CR2/KR2
  • On
  • Off
 Off Sets the value of the override consortium low-latency FEC ability field, bit 5 of Register 0xCC.
LL FEC Ability for 200G BASE-CR4/KR4
  • On
  • Off
 Off Sets the value of the override consortium low-latency FEC ability field, bit 6 of Register 0xCC.
Advertise IEEE Port Ability
10G BASE-KR(A2)
  • On
  • Off
 Off Sets the value of the override IEEE port ability fields, bit 12 of Register 0xCC.
40G BASE-KR4 (A3)
  • On
  • Off
 Off Sets the value of the override IEEE port ability fields, bit 13 of Register 0xCC.
40G BASE-CR4 (A4)
  • On
  • Off
 Off Sets the value of the override IEEE port ability fields, bit 14 of Register 0xCC.
100G BASE-KR4(A7)
  • On
  • Off
 Off Sets the value of the override IEEE port ability fields, bit 15 of Register 0xCC.
100G BASE-CR4(A8)
  • On
  • Off
 Off Sets the value of the override IEEE port ability fields, bit 16 of Register 0xCC.
25G BASE-KR-S/CR-S/A9
  • On
  • Off
 Off Sets the value of the override IEEE port ability fields, bit 17 of Register 0xCC.
25G BASE-KR-CR-A10
  • On
  • Off
 Off Sets the value of the override IEEE port ability fields, bit 18 of Register 0xCC.
50G BASE-KR-CR(A13)
  • On
  • Off
 Off Sets the value of the override IEEE port ability fields Bit 19 of Register 0xCC.
100G BASE-KR2/CR2(A14)
  • On
  • Off
 Off Sets the value of the override IEEE port ability fields, bit 20 of Register 0xCC.
200G BASE-KR/CR4(A15)
  • On
  • Off
 Off Sets the value of the override IEEE port ability fields, bit 21 of Register 0xCC.
100G BASE-KR/CR(A16)
  • On
  • Off
 Off Sets the value of the override IEEE port ability fields, bit 22 of Register 0xCC.
200G BASE -KR2/CR2 (A17)
  • On
  • Off
 Off Sets the value of the override IEEE port ability fields,bit 23 of Register 0xCC.
400G BASE - KR4/CR4
  • On
  • Off
 Off Sets the value of the override IEEE port ability fields, bit 29 of Register 0xCC.
Advertise Consortium Port Ability
25G BASE-KR1 (D20)
  • On
  • Off
 Off Sets the value of the override consortium port ability fields, bit 24 of Register 0xCC.
25G BASE-CR1 (D21)
  • On
  • Off
 Off Sets the value of the override consortium port ability fields, bit 25 of Register 0xCC.
50 BASE-KR2 (D24)
  • On
  • Off
 Off Sets the value of the override consortium port ability fields,bit 26 of Register 0xCC.
50 BASE-CR2 (D25)
  • On
  • Off
 Off Sets the value of the override consortium port ability fields, bit 27 of Register 0xCC.
400G BASR-KR8/CR8 (D34)
  • On
  • Off
 Off Sets the value of the override consortium port ability fields, bit 28 of Register 0xCC.
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