Quartus Prime Pro Edition Help version 17.1

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  • Welcome to the Intel® Quartus® Prime Pro Edition Software
    • Intel® Quartus® Prime Pro Edition Highlights
    • New Features in this Release
    • Terminology
    • Using Help Effectively
      • Opening the Glossary
      • Opening the Messages List
      • Using the Search
  • Starting the Intel® Quartus® Prime Software (quartus.exe) From the Command Line
  • Options Dialog Box
    • General Page (Options Dialog Box)
    • Fonts Page (Options Dialog Box) (All Editors)
    • Headers & Footers Settings (Options Dialog Box)
    • Internet Connectivity Page (Options Dialog Box)
    • Block/Symbol Editor Page (Options Dialog Box)
    • Libraries Page (Options Dialog Box)
    • Design Templates (Options Dialog Box)
    • License Setup Page (Options Dialog Box)
    • Preferred Text Editor (Options Dialog Box)
    • Processing Page (Options Dialog Box)
    • Tooltip Settings Page (Options Dialog Box)
    • Messages Page (Options Dialog Box)
    • Memory Editor Page (Options Dialog Box)
    • Colors Page (Options Dialog Box) (All Editors)
    • Resource Property Editor Page (Options Dialog Box)
    • Text Editor Page (Options Dialog Box)
    • General Settings for IP
  • Managing Projects
    • Viewing Project Information
      • Project Navigator Window
        • Hierarchy tab
        • Files tab
        • Design Units tab
          • Design Unit Properties Dialog Box (Shortcut Menu)
        • IP Components Tab
          • Edit in Parameter Editor Command (Shortcut Menu)
        • Open in Main Window Command (Shortcut Menu)
      • Compilation Dashboard
    • Managing Project Settings
      • quartus2.ini File
      • Settings Dialog Box
        • General Page (Settings Dialog Box)
          • Revision Type
        • Files Page (Settings Dialog Box)
        • Libraries Page (Settings Dialog Box)
        • General Settings for IP
        • Operating Settings and Conditions Page (Settings Dialog Box)
          • Voltage Page (Settings Dialog Box)
          • Temperature Page (Settings Dialog Box)
        • Compilation Process Settings Page (Settings Dialog Box)
          • More Compilation Process Settings Dialog Box
        • EDA Tool Settings Page (Settings Dialog Box)
          • Design Entry/Synthesis (Settings Dialog Box)
          • Simulation (Settings Dialog Box)
            • Format for output netlist
            • Output Directory
            • Use Partial Line Selection
            • More EDA Netlist Writer Settings Dialog Box
          • Board-level signal integrity analysis
        • Compiler Settings Page (Settings Dialog Box)
          • Advanced Synthesis Settings Dialog Box
          • Advanced Fitter Settings Dialog Box
          • VHDL Input Page (Settings Dialog Box)
          • Verilog HDL Input Page (Settings Dialog Box)
          • Default Parameters Page (Settings Dialog Box)
        • Timing Analyzer Page (Settings Dialog Box)
          • SDC files to include in the project
          • Report worst-case paths during compilation
          • Tcl Script File for customizing reports during compilation
          • Metastability Analysis
        • Assembler Page (Settings Dialog Box)
        • Signal Tap Logic Analyzer Page (Settings Dialog Box)
        • Logic Analyzer Interface Page (Settings Dialog Box)
        • Power Analyzer Settings Page (Settings Dialog Box)
    • Using Project Revisions
      • Revisions Dialog Box
      • Create Revision Dialog Box
    • Archiving Projects
      • Advanced Archive Settings Dialog Box
      • Archive Project Dialog Box
    • Managing Project Databases
  • Global Menu Items and Dialog Boxes
    • File Menu
      • Intel® Quartus® Prime Incompatible Project Dialog Box
      • Save Project Command (File Menu)
      • Open Dialog Box
      • Page Setup Dialog Box
      • Print Dialog Box
      • Select Family Dialog Box
    • Edit Menu
    • View Menu
    • Project Menu
      • Add Current File to Project Command (Project Menu)
      • Upgrade IP Components Dialog Box (Project Menu)
    • Assignments Menu
      • Export Assignments Dialog Box
    • Processing Menu
      • Start Compilation Command (Processing Menu)
      • Start Timing Analyzer Command (Processing Menu)
        • Start Analysis & Synthesis Command (Processing Menu)
        • Start Fitter Commands (Processing Menu)
        • Start Assembler Command (Processing Menu)
        • Start Timing Analyzer Command (Processing Menu)
        • Start Power Analyzer Command (Processing Menu)
      • Update Memory Initialization File Command (Processing Menu)
      • Compilation Report Command (Processing Menu)
      • Power Analyzer Tool Window
    • Tools Menu
      • Generate Simulation Setup Script for IP (Tools Menu)
      • Launch Simulation Library Compiler (Tools Menu)
      • Launch Design Space Explorer Command (Tools Menu)
      • Timing Analyzer Command (Tools Menu)
      • Advisors
        • Timing Optimization Advisor Command (Tools Menu)
        • Power Optimization Advisor Command (Tools Menu)
        • Compilation Time Advisor Command (Tools Menu)
      • Chip Planner Command (Tools Menu)
      • Design Partition Planner Command (Tools Menu)
      • Interface Planner Command (Tools Menu)
      • Netlist Viewers
        • RTL Viewer Command (Tools Menu)
        • Technology Map Viewer Command (Tools Menu)
      • Logic Analyzer Interface Editor (Tools Menu)
      • In-System Sources and Probes Editor (Tools Menu)
      • Signal Tap Logic Analyzer Window (Tools Menu)
      • Programmer (Tools Menu)
      • JTAG Chain Debugger Command (Tools Menu)
      • Fault Injection Debugger (Tools Menu)
      • System Debugging Tools
        • System Console (Tools Menu)
        • Transceiver Toolkit Command (Tools Menu)
        • External Memory Interface Toolkit (Tools Menu)
      • IP Catalog (Tools Menu)
      • Tcl Scripts (Tools Menu)
      • Customize
        • Customize Toolbar Dialog Box
      • Nios® II Software Build Tools for Eclipse (Tools Menu)
    • Window Menu
    • Task Window
      • Tcl Scripts Dialog Box (Tasks Window)
      • Customize Flow Dialog Box (Tasks Window)
    • Use Existing Project Settings Dialog Box (New Project Wizard)
      • Use settings from last opened project
    • Add Node to Signal Tap Logic Analyzer Command (Shortcut Menu)
    • Zoom Dialog Box
    • Copy Full Path Command (Right-Click Menu)
    • Export Dialog Box (All Editors)
    • Find/Replace Dialog Boxes (All Other Editors)
      • Find what
    • Copy File Name Command (Right-Click Menu)
  • Running Timing Analysis
    • File Menu
      • New SDC File Command (Timing Analyzer)
      • Open SDC File Command (Timing Analyzer)
    • Netlist Menu
      • Set Operating Conditions Dialog Box (set_operating_conditions)
    • Reports Menu
      • Report CDC Viewer Command
        • Report Custom CDC Viewer Command
    • Tasks Pane
      • Read SDC File Command
      • Report Timing Dialog Box
      • Report Minimum Pulse Width Dialog Box
      • Report False Path Dialog Box
      • Report Path Dialog Box
      • Report Exceptions Dialog Box
      • Report Bottlenecks Dialog Box
      • Report Net Timing Dialog Box
      • Report Skew Dialog Box (report_skew)
      • Report Max Skew Dialog Box (report_max_skew)
      • Report Net Delay
      • Report Metastability Command
      • Report Recovery Summary Command
      • Report Removal Summary Command
      • Report Timing Closure Recommendations Dialog Box
    • Constraints Menu
    • Script Menu
    • View Menu
    • Tools Menu
  • Timing Analysis Settings
    • Timing Analyzer Page (Settings Dialog Box)
    • Set Clock Groups Dialog Box (set_clock_groups)
    • Set Clock Latency Dialog Box (set_clock_latency)
    • Set Clock Uncertainty Dialog Box (set_clock_uncertainty)
    • Set False Path Dialog Box (set_false_path)
    • Set Input Delay Dialog Box (set_input_delay)
    • Set Output Delay Dialog Box (set_output_delay)
    • Set Maximum Delay Dialog Box (set_max_delay)
    • Set Minimum Delay Dialog Box (set_min_delay)
    • Set Multicycle Path Dialog Box (set_multicycle_path)
  • ::quartus::sdc
    • all_clocks (::quartus::sdc)
    • all_inputs (::quartus::sdc)
    • all_outputs (::quartus::sdc)
    • all_registers (::quartus::sdc)
    • derive_clocks (::quartus::sdc)
    • get_cells (::quartus::sdc)
    • get_clocks (::quartus::sdc)
    • get_nets (::quartus::sdc)
    • get_pins (::quartus::sdc)
    • get_ports (::quartus::sdc)
    • remove_clock_groups (::quartus::sdc)
    • remove_clock_latency (::quartus::sdc)
    • remove_clock_uncertainty (::quartus::sdc)
    • remove_disable_timing (::quartus::sdc)
    • remove_input_delay (::quartus::sdc)
    • remove_output_delay (::quartus::sdc)
    • reset_design (::quartus::sdc)
    • set_input_transition (::quartus::sdc)
    • set_disable_timing (::quartus::sdc)
  • ::quartus::sdc_ext
    • get_active_clocks (::quartus::sdc_ext)
    • get_assignment_groups (::quartus::sdc_ext)
    • get_fanins (::quartus::sdc_ext)
    • get_fanouts (::quartus::sdc_ext)
    • get_keepers (::quartus::sdc_ext)
    • get_nodes (::quartus::sdc_ext)
    • get_partitions (::quartus::sdc_ext)
    • get_registers (::quartus::sdc_ext)
    • remove_annotated_delay (::quartus::sdc_ext)
    • reset_timing_derate (::quartus::sdc_ext)
    • set_active_clocks (::quartus::sdc_ext)
    • set_annotated_delay (::quartus::sdc_ext)
    • set_max_skew (::quartus::sdc_ext)
    • set_net_delay (::quartus::sdc_ext)
    • set_scc_mode (::quartus::sdc_ext)
    • set_time_format (::quartus::sdc_ext)
    • set_timing_derate (::quartus::sdc_ext)
  • ::quartus::sta
    • add_to_collection (::quartus::sta)
    • check_timing (::quartus::sta)
    • create_report_histogram (::quartus::sta)
    • create_slack_histogram (::quartus::sta)
    • create_timing_netlist (::quartus::sta)
    • create_timing_summary (::quartus::sta)
    • delete_timing_netlist (::quartus::sta)
    • delete_sta_collection (::quartus::sta)
    • enable_ccpp_removal (::quartus::sta)
    • enable_sdc_extension_collections (::quartus::sta)
    • get_available_operating_conditions (::quartus::sta)
    • get_cell_info (::quartus::sta)
    • get_clock_domain_info (::quartus::sta)
    • get_clock_fmax_info (::quartus::sta)
    • get_clock_info (::quartus::sta)
    • get_datasheet (::quartus::sta)
    • get_default_sdc_file_names (::quartus::sta)
    • get_edge_info (::quartus::sta)
    • get_edge_slacks (::quartus::sta)
    • get_entity_instances (::quartus::sta)
    • get_min_pulse_width (::quartus::sta)
    • get_net_info (::quartus::sta)
    • get_node_info (::quartus::sta)
    • get_object_info (::quartus::sta)
    • get_operating_conditions (::quartus::sta)
    • get_operating_conditions_info (::quartus::sta)
    • get_partition_info (::quartus::sta)
    • get_path (::quartus::sta)
    • get_path_info (::quartus::sta)
    • get_pin_info (::quartus::sta)
    • get_point_info (::quartus::sta)
    • get_port_info (::quartus::sta)
    • get_register_info (::quartus::sta)
    • get_timing_paths (::quartus::sta)
    • locate (::quartus::sta)
    • query_collection (::quartus::sta)
    • read_sdc (::quartus::sta)
    • register_delete_timing_netlist_callback (::quartus::sta)
    • remove_from_collection (::quartus::sta)
    • report_advanced_io_timing (::quartus::sta)
    • report_bottleneck (::quartus::sta)
    • report_clock_fmax_summary (::quartus::sta)
    • report_clock_transfers (::quartus::sta)
    • report_clocks (::quartus::sta)
    • report_datasheet (::quartus::sta)
    • report_ddr (::quartus::sta)
    • report_max_skew (::quartus::sta)
    • report_metastability (::quartus::sta)
    • report_min_pulse_width (::quartus::sta)
    • report_ini_usage (::quartus::sta)
    • report_net_delay (::quartus::sta)
    • report_net_timing (::quartus::sta)
    • report_partitions (::quartus::sta)
    • report_path (::quartus::sta)
    • report_rskm (::quartus::sta)
    • report_sdc (::quartus::sta)
    • report_skew (::quartus::sta)
    • report_timing (::quartus::sta)
    • report_timing_tree (::quartus::sta)
    • report_tccs (::quartus::sta)
    • report_ucp (::quartus::sta)
    • set_operating_conditions (::quartus::sta)
    • timing_netlist_exist (::quartus::sta)
    • update_timing_netlist (::quartus::sta)
    • use_timequest_style_escaping (::quartus::sta)
    • write_sdc (::quartus::sta)
  • Integrating Other EDA Tools
    • About Integrating Other EDA Tools
    • Creating and Instantiating Intel® Quartus® Prime IP Cores in Other EDA Tools
    • Generating a Test Bench Template for Use with Other EDA Tools
      • Test Benches Dialog Box
    • Design Entry/Synthesis Tools
      • Using the Precision RTL Synthesis Software with the Intel® Quartus® Prime Software
        • Setting Up the Precision RTL Synthesis Working Environment
        • Creating a Design for Use with the Precision RTL Synthesis Software
        • Setting Up a Project with the Precision RTL Synthesis Software
        • Assigning Design Constraints with the Precision RTL Synthesis Software
        • Generating EDIF Netlist Files with the Precision RTL Synthesis Software
      • Synplify Software
        • Synopsys® -Provided Logic Libraries
        • Setting Up the Synplify Working Environment
        • Creating a Design for Use with the Synplify Software
      • Celoxica
        • Setting Up the DK Design Suite Working Environment
    • About Simulating Designs
      • Simulator Support
      • Simulation Flows
      • Intel® Quartus® Prime Simulation Models
      • Compiling Intel FPGA simulation model files
      • Running EDA Simulators
        • Active-HDL
        • ModelSim® - Intel® FPGA Edition
          • Setting Up a ModelSim® - Intel® FPGA Edition Project
          • Performing a Functional Simulation with the ModelSim® - Intel® FPGA Edition Software
          • Performing a Timing Simulation with the ModelSim® - Intel® FPGA Edition Software
        • QuestaSim
          • Setting Up a Project with the QuestaSim Software
          • Compiling Libraries and Design Files with the QuestaSim Software
          • Performing a Functional Simulation with the QuestaSim Software
          • Performing a Timing Simulation with the QuestaSim Software
        • Riviera Pro
        • VCS
        • VCS MX
          • Performing a Functional Simulation with the VCS MX Software
          • Performing a Timing Simulation with the VCS MX (VHDL) Software
    • Generating Output Files for Board-Level Tools
      • Generating Board-Level Timing Analysis Files
        • Setting Up the Tau Working Environment
        • Creating Stamp Model Files with the Intel® Quartus® Prime Software
        • Performing Timing Verification with the Tau Software
      • Generating Board-Level Symbol Output Files
        • Generating FPGA Xchange-Format Files for Use with Other EDA Tools
        • Generating PartMiner edaXML-Format Files for Use with Other EDA Tools
      • Generating Board-Level Signal Integrity Analysis Files
        • Generating HSPICE Simulation Deck Files for External Signal Integrity Analysis
      • Generating Boundary-Scan Description Language Files
        • Create Board-Level Boundary-Scan File Window (File Menu)
  • Using Project Revisions
    • Revisions Dialog Box
    • Create Revision Dialog Box
  • Archiving Projects
    • Advanced Archive Settings Dialog Box
    • Archive Project Dialog Box
  • Managing Project Databases
  • Creating Designs
    • Using the Block Editor
      • Block/Symbol Editor Page (Options Dialog Box)
        • Snap to Grid (applies only to Symbol Editor)
        • Use Rubberbanding
        • Use Partial Line Selection
        • Double-click to show property sheet
        • Show Connection Rectangle
        • Include a Border When Printing
        • Automatically Open as Detached Window
      • Arc Properties Dialog Box
      • Show Commands (View Menu)
      • AutoFit Command
      • Block Diagram/Schematic File (New Dialog Box)
      • Block Symbol File (New Dialog Box)
      • Block Properties Dialog Box (Shortcut Menu)
      • Bus Properties Dialog Box
      • Circle Properties Dialog Box
      • Conduit Properties Dialog Box
      • Constant Properties Dialog Box
      • Create Design File from Selected Block Dialog Box
      • Create HDL Design File for Current File Dialog Box
      • Edit Selected Symbol Command (Shortcut Menu)
      • Flip Commands (Edit Menu)
      • Line Commands (Edit Menu)
      • Rotate Commands (Edit Menu)
      • Generate Pins for Symbol Ports Command
      • Insert Symbol and Insert Symbol as Block Dialog Boxes
      • Line Properties Dialog Box
      • Mapper Properties Dialog Box
      • Multipage Setup Dialog Box
      • Node Properties Dialog Box (Block Editor)
      • Properties Dialog Box (Block & Symbol Editors)
      • Open Design File Command (Shortcut Menu)
      • Parameter Properties Dialog Box
      • Pin Properties Dialog Box
      • Port Properties Dialog Box
      • Rectangle Properties Dialog Box
      • Format Tab (Properties Command)
      • Font Tab (Properties Command)
    • Using the Memory Editor
      • Memory Editor Page (Options Dialog Box)
      • New Memory Initialization File Command (Intel® Quartus® Prime Menu)
      • Insert Cells Command (Edit Menu)
      • Paste Insert Command (Edit Menu)
      • Reverse Address Contents Command (Edit Menu)
      • Fill Commands (Edit Menu) (Memory Editor)
      • Address Radix Commands (View Menu)
      • Cells Per Row Commands (View Menu)
      • Memory Radix Commands (View Menu)
      • Show ASCII Equivalents Command (View Menu)
      • Show Delimiter Spaces Command (View Menu)
      • Update Current Memory with Simulation Data Command (Processing Menu)
      • Update Memory Initialization File Command (Processing Menu)
      • Custom Fill Cells Dialog Box
      • Go To Dialog Box
      • Open Memory Dialog Box
      • Memory Size Wizard: Change Number of Word and Word Size Dialog Box
      • Number of Words & Word Size Dialog Box
    • Using the Text Editor
      • Autocomplete Text Command (Edit Menu)
      • Clear All Bookmarks (Current) Command (Edit Menu)
      • Clear All Bookmarks (All Files) Command (Edit Menu)
      • Comment Selection Command (Shortcut Menu)
      • Decrease Indent Command (Edit Menu)
      • Duplicate View Command (Shortcut Menu)
      • Find Matching Delimiter Command (Edit Menu)
      • Go To Dialog Box (Edit Menu)
      • Increase Indent Command (Edit Menu)
      • Show Indentation Guide Command (View Menu)
      • Insert Constraint Command (Shortcut Menu)
      • Insert File Command (Edit Menu)
      • Insert Template Dialog Box
      • Jump To Next Bookmark Command (Edit Menu)
      • Jump To Previous Bookmark Command (Edit Menu)
      • Show Line Numbers Command (View Menu)
      • Word Wrap Command (View Menu)
      • Open AHDL Include File Command (Shortcut Menu)
      • Open Symbol File Command (Shortcut Menu)
      • Preferred Text Editor (Options Dialog Box)
      • Replace Tabs With Spaces Command (Edit Menu)
      • Show White Space Command (View Menu)
      • Split Window Command (Shortcut Menu)
      • Toggle Bookmark Command (Edit Menu)
      • Uncomment Selection Command (Shortcut Menu)
      • Save User Template Dialog Box
      • User Template Directory Dialog Box
      • Text Editor Page (Options Dialog Box)
  • Using HDL with the Intel® Quartus® Prime Software
    • Intel® Quartus® Prime Primitives
      • Primitives
      • List of Primitives
        • ALT_BIDIR_BUF Primitive
        • ALT_INBUF Primitive
        • ALT_INBUF_DIFF Primitive
        • ALT_IOBUF Primitive
        • ALT_OUTBUF Primitive
        • ALT_OUTBUF_DIFF Primitive
        • ALT_OUTBUF_TRI Primitive
        • AND Primitive
        • BAND (Block Design Files only) Primitive
        • BIDIR or INOUT Primitive/Port
        • BNAND (Block Design Files only) Primitive
        • BNOR (Block Design Files only) Primitive
        • BOR (Block Design Files only) Primitive
        • CARRY_SUM Primitive
        • CASCADE Primitive
        • CONSTANT Primitive
        • DFF Primitive
        • DFFE Primitive
        • DLATCH Primitive
        • EXP Primitive
        • GLOBAL Primitive
        • GND (Block Design Files only) Primitive
        • INPUT or IN Primitive/Port
        • JKFF Primitive
        • JKFFE Primitive
        • LATCH Primitive
        • LCELL Primitive
        • LUT_INPUT Primitive
        • LUT_OUTPUT Primitive
        • NAND Primitive
        • NOR Primitive
        • NOT Primitive
        • OPNDRN Primitive
        • OR Primitive
        • PARAM Primitive
        • Primitive/Port Interconnections
        • SOFT Primitive
        • SRFF Primitive
        • SRFFE Primitive
        • TFF Primitive
        • TFFE Primitive
        • Title Block Primitive
        • TRI Primitive
        • Unused Inputs to Primitives, Megafunctions & Macrofunctions
        • VCC (Block Design Files only) Primitive
        • WIRE (Block Design Files only) Primitive
        • XNOR Primitive
        • XOR Primitive
        • Pinstub Names in Primitives
        • WYSIWYG Atom Names Unavailable for Use as Primitive Instance Names
    • Managing IP in Intel® Quartus® Prime
      • About the IP Catalog and Parameter Editor
      • Megafunctions/LPM
  • HDL Language Support
  • Working with Qsys Pro
    • Qsys Pro Component Editor
      • Add Commands (Templates Menu) (Component Editor)
      • Platform Designer Component Editor
      • Template Command (Platform Designer Component Editor)
      • Files Tab (Platform Designer Component Editor)
      • Parameters Tab (Platform Designer Component Editor)
      • Interfaces Tab (Platform Designer Component Editor)
    • Working with Presets in Qsys Pro
      • New Preset Dialog Box (Platform Designer)
      • Presets Tab (Platform Designer)
      • Update Preset Dialog Box (Platform Designer)
    • Create a Qsys Pro System
      • Add Commands (Templates Menu) (Component Editor)
      • Custom Layouts (View Menu) (Platform Designer)
      • Interconnect Requirements Tab (View Menu) (Platform Designer)
      • Messages Tab (View Menu) (Platform Designer)
      • New Component Command (File Menu) (Platform Designer)
      • New System Command (File Menu) (Platform Designer)
      • Add Instance Dialog Box (Platform Designer)
      • Create Snythesis File From Signals Dialog Box (Platform Designer)
      • IP Catalog (View Menu) (Platform Designer)
    • Qsys Pro Commands
      • Assign Custom Instruction Opcodes Command (System Menu) (Platform Designer)
      • Assign Base Addresses Command (System Menu) (Platform Designer)
      • Assign Interrupt Numbers (System Menu) (Platform Designer)
      • Browse Project Directory (File Menu) (Platform Designer)
      • Archive System (File Menu)
      • Restore Archived System (File Menu)
      • Export System as qsys script (.tcl) (File menu)
      • Synchronize IP File References (File Menu)
      • Create Global Reset Network Command (System Menu) (Platform Designer)
      • Generate Example Design (Generate Menu) (Platform Designer)
      • Lock/Unlock Base Address Commands (Edit Menu) (Platform Designer)
      • Nios® II Software Build Tools for Eclipse Command (Tools Menu) (Platform Designer)
      • Nios® II Command Shell [gcc4] Command (Tools Menu) (Platform Designer)
      • IP Search Path Options (Tools Menu)
      • Parameters Tab (View Menu) (Platform Designer)
      • Recent Projects (File Menu) (Platform Designer)
      • Refresh System Command (File Menu) (Platform Designer)
      • Remove Dangling Connections Command (System Menu) (Platform Designer)
      • Reset to IP Layout (View Menu) (Platform Designer)
      • Reset to System Layout (View Menu) (Platform Designer)
      • Show System With Platform Designer Interconnect Command (System Menu) (Platform Designer)
      • Options Dialog Box (Tools Menu) (Platform Designer)
    • View a Qsys Pro System
      • Assignments Tab (View Menu) (Platform Designer)
      • Block Symbol Tab (View Menu) (Platform Designer)
      • Connections Tab (View Menu) (Platform Designer)
      • Custom Layouts (View Menu) (Platform Designer)
      • Element Docs Tab (Platform Designer)
      • Hierarchy Tab (View Menu) (Platform Designer)
      • Device Family Tab (View Menu) (Platform Designer)
      • Parameters Tab (View Menu) (Platform Designer)
      • Reset Domains (View Menu) (Platform Designer)
      • Schematic Tab (View Menu) (Platform Designer)
      • Set Color (Edit Menu) (Platform Designer)
      • Clock Domains (View Menu) Platform Designer)
      • Avalon Memory Mapped Domains (View Menu) (Platform Designer)
      • Create Snythesis File From Signals Dialog Box (Platform Designer)
      • Address Map Tab (View Menu) (Platform Designer)
      • System Contents Tab (View Menu) (Platform Designer)
      • Component Instantiation Editor (Component Instantiation Tab)
      • Interface Requirements Tab
      • System Info Tab
      • System Scripting (View Menu) (Platform Designer)
      • Validate Component Footprint
      • Validate System Integrity
    • Generate in Qsys Pro
      • Generate Example Design (Generate Menu) (Platform Designer)
      • Generate Testbench System (Generate Menu) (Platform Designer)
      • Generate HDL (Generate Menu) (Platform Designer)
      • Generate Example Design (Generate Menu) (Platform Designer)
    • Debug in Qsys Pro
      • Instrumentation Tab (View Menu) (Platform Designer)
  • Node Finder (View Menu)
    • New Custom Filter Dialog Box
    • Customize Filter Dialog Box
    • Select Hierarchy Level Dialog Box
  • Assignments
    • Assignment Editor (Assignments Menu)
      • Location Dialog Box
      • Customize Columns Dialog Box
    • Pin Planner Command (Assignments Menu)
    • Remove Assignments Dialog Box (Assignments Menu)
    • Back-Annotate Assignments Dialog Box
      • Node Filter Dialog Box
    • Import Assignments Dialog Box (Assignments Menu)
      • Assignment Categories Dialog Box
      • Advanced Import Settings Dialog Box
  • BluePrint Planning
    • Interface Planner Flow Control
    • Interface Planner Assignments Tab
    • Interface Planner Home Tab
    • Interface Plan Tab
    • Interface Planner Reports Tab
  • Manage I/O Pins
    • Pin Planner Options Page
    • Create Top-Level Design File Dialog Box
    • Assign Up, Down, Right, Left, and One by One Commands (Edit Menu)
      • Early Pin Planning Dialog Box
    • Pin Legend Window (View Menu)
    • Set Up Top-Level Design File Window (Edit Menu)
    • Show Commands (View Menu/Task Window) (Pin Planner)
    • Groups List Command (View Menu)
      • Edit Intel® FPGA IP (Shortcut Menu)
    • All Pins List Command (View Menu)
      • Customize Filter Dialog Box
      • New Filter Dialog Box
    • Pad View Window (View Menu)
    • Board Trace Model Window (View Menu)
    • Pin Migration View Window (View Menu)
      • Show Commands (Shortcut Menu) (Pin Migration View Window)
    • Resources Window (View Menu)
    • Task and Report Windows (Pin Planner)
    • Find Swappable Pins Dialog Box
    • Pin Finder Dialog Box
    • Group Dialog Boxes
    • Reserve Commands (Shortcut Menu)
    • Show Assignable Pins (Shortcut Menu)
    • Properties Dialog Boxes
  • Using Advisors for Design Optimization
    • About Advisors in the Intel® Quartus® Prime Software
    • Intel® Arria® 10 to Intel® Stratix® 10 Migration Advisor Command (Tools Menu)
    • Compilation Time Advisor Command (Tools Menu)
    • Power Optimization Advisor Command (Tools Menu)
    • Timing Optimization Advisor Command (Tools Menu)
  • Intel® Quartus® Prime Reports
    • Managing Reports
      • Navigating the Report Window
        • To Expand or Collapse a Folder in the Report Window Contents
        • To Open Multiple Report Windows
      • Manipulating Compilation or Simulation Report Window Output
        • SEU FIT Report
        • Simulation Flow Reports
        • Legal Notice Section (Compilation or Simulation Report)
      • Aligning Text
      • Copying text, charts, table cells, hierarchy entity names and speed performance table rows in reports:
      • Printing the results of a compilation or simulation report:
      • Reordering and Hiding Columns in the Report Window
      • Saving a report window messages or logical memories section:
      • Saving a report table
      • Selecting reports to print
      • Include Report Section in Print List Command
      • Compilation Report Command (Processing Menu)
      • Print Command (Report Window)
      • Save Current Report Section As Command
    • Compilation Reports
      • Synthesis Reports
        • Synthesis Summary Reports
        • Synthesis Settings Reports
        • Parallel Compilation Report
        • Synthesis Source Files Read Report
        • Source Assignments Report
        • Parameter Settings by Entity Instance Report
        • Synthesis Optimization Results Reports
        • Synthesis Partition Reports
        • Synthesis Connectivity Checks Report
        • Synthesis Resources Reports
        • State Machines Report
        • Equations Report
          • Note (1)
        • Partition Merge Reports
      • Fitter Summary Report
        • Plan Stage Reports
        • Early Place Stage Reports
        • Place Stage Reports
        • Route Stage Reports
        • Retime Stage Reports
        • Finalize Stage Reports
        • Fitter Resources Reports
        • Clock Fmax Summary Report
        • Fitter I/O Rules Reports
      • Debug Tools Setting Summary Reports
      • Timing Analyzer Multicorner Timing and Timing Model Datasheet Reports
      • Power Analyzer Reports
        • Early Power Estimator File Generator Reports
      • Assembler Reports
      • EDA Netlist Writer Reports
  • Viewing Messages
    • About the Messages window
    • Message Suppression Manager Dialog Box
    • Messages Page (Options Dialog Box)
    • Clear Messages from Window Command (Shortcut Menu)
    • Clear All Flags Command (Shortcut Menu)
    • Clear Flag Command (Shortcut Menu)
    • Flag Message Command (Shortcut Menu)
    • Hide Previous Compilation Messages Command (Shortcut Menu)
    • Load Messages from the Compilation Report (Shortcut Menu)
    • Save Messages Command (Shortcut Menu)
    • Select Text Command (Shortcut Menu)
    • Show All Submessages Command (Shortcut Menu)
    • Clear Sorting Command (Shortcut Menu)
    • Suppress All Flagged Messages Command (Shortcut Menu)
    • Suppress Messages with Matching ID Command (Shortcut Menu)
    • Suppress Messages with Matching Keyword Command (Shortcut Menu)
    • Suppress Message Command (Shortcut Menu)
    • Export Message Flag Rule File Dialog Box
    • Export Message Suppression Rule File Dialog Box
    • Import Message Flag Rule File Dialog Box
    • Import Message Suppression Rule File Dialog Box
    • Suppress by Keyword Dialog Box
  • Compilation
    • Compiling Designs
      • Compilation Dashboard
      • Start Compilation Command (Processing Menu)
      • Start Analysis & Synthesis Command (Processing Menu)
      • Start Fitter Commands (Processing Menu)
      • Start Assembler Command (Processing Menu)
    • Compiler Settings
      • Device Page (Settings Dialog Box)
        • Board Page (Settings Dialog Box)
      • Device and Pin Options Dialog Box
        • General Page (Device and Pin Options Dialog Box)
          • Delay Entry to User Mode
          • Configuration Clock Source
        • Configuration Page (Device and Pin Options Dialog Box)
        • Programming Files Page (Device and Pin Options Dialog Box)
        • Unused Pins Page (Device and Pin Options Dialog Box)
        • Dual-Purpose Pins Page (Device and Pin Options Dialog Box)
        • Board Trace Model Page (Device and Pin Options Dialog Box)
        • I/O Timing Page (Device and Pin Options Dialog Box)
        • Voltage Page (Device and Pin Options Dialog Box)
        • Error Detection CRC Page (Device and Pin Options Dialog Box)
        • CvP Settings Page (Device and Pin Options Dialog Box)
        • Partial Reconfiguration Page (Device and Pin Options Dialog Box)
        • Power Management & VID Page
      • Compiler Settings Page (Settings Dialog Box)
        • Advanced HyperFlex Settings
        • Advanced Synthesis Settings Dialog Box
      • Migration Devices Dialog Box
      • Recommendations Dialog Box
      • Device Page (Settings Dialog Box)
        • Board Page (Settings Dialog Box)
      • Device and Pin Options Dialog Box
        • General Page (Device and Pin Options Dialog Box)
          • Delay Entry to User Mode
          • Configuration Clock Source
        • Configuration Page (Device and Pin Options Dialog Box)
        • Programming Files Page (Device and Pin Options Dialog Box)
        • Unused Pins Page (Device and Pin Options Dialog Box)
        • Dual-Purpose Pins Page (Device and Pin Options Dialog Box)
        • Board Trace Model Page (Device and Pin Options Dialog Box)
        • I/O Timing Page (Device and Pin Options Dialog Box)
        • Voltage Page (Device and Pin Options Dialog Box)
        • Error Detection CRC Page (Device and Pin Options Dialog Box)
        • CvP Settings Page (Device and Pin Options Dialog Box)
        • Partial Reconfiguration Page (Device and Pin Options Dialog Box)
        • Power Management & VID Page
      • Compiler Settings Page (Settings Dialog Box)
        • Advanced Synthesis Settings Dialog Box
      • Migration Devices Dialog Box
      • Recommendations Dialog Box
  • Synthesis
    • Start Analysis & Synthesis Command (Processing Menu)
  • Partial Reconfiguration
    • Design Partitions Window
    • Set As Design Partition Command (Shortcut Menu)
    • Export Design Partition Dialog Box
  • Place and Route
    • Start Fitter Commands (Processing Menu)
  • Generating Programming Files
    • Start Assembler Command (Processing Menu)
    • Assembler Page (Settings Dialog Box)
    • Add JTAG ID Dialog Box
    • Export User-Defined Device Dialog Box
    • Import User Devices Dialog Box
    • Edit Device Dialog Box
    • Add Hex Data Dialog Box
    • Hexadecimal File Options Dialog Box
    • Hardware Setup Dialog Box
    • Open JTAG Chain Log File Dialog Box
    • New CFI Flash Device Dialog Box
    • New Device Dialog Box
    • OpenCore Plus Status Dialog Box
    • PMSF File Properties Dialog Box
    • Select Device Dialog Box
    • Select Flash Device Dialog Box
    • Select New Flash Device Dialog Box
    • SOF Data Properties Dialog Box
    • SOF File Properties Dialog Box
    • Add Hardware Dialog Box
    • Add Server Dialog Box
    • Configure Local JTAG Server Dialog Box
    • Convert Programming Files - Advanced Options Dialog Box
    • Define CFI Flash Device Dialog Box
    • Device's Properties Dialog Box
    • Select Devices Dialog Box
    • Select Programming File Dialog Box
    • Select I/O Pin State File Dialog Box
    • Auto Detect Command (Processing Menu)
    • Select New Device Dialog Box
    • Select New Programming File Dialog Box
    • Select New I/O Pin State File Dialog Box
    • Select POF Dialog Box
    • Convert Programming Files Dialog Box
    • Create JAM, JBC, SVF, or ISC File Dialog Box
    • Define CFI Flash Device Command
    • Delete POF Command (Edit Menu)
    • Delete IPS File Command (Edit Menu) (Programmer)
    • Flash Device Commands (Edit Menu)
    • ISP CLAMP State Editor Window (File Menu)
    • JTAG Chain Debugger Command (Tools Menu)
    • Programmer Options Dialog Box
    • Properties Dialog Box (Programmer)
    • Save Data To File As Dialog Box
    • Show Device Tree/Pane
    • Programmer (Tools Menu)
  • Debugging your Design
    • Debugging with the Signal Tap Logic Analyzer
      • Signal Tap Logic Analyzer Options Dialog Box
      • View Page (Signal Tap Logic Analyzer) (Options Dialog Box)
        • Signal Tap Logic Analyzer Page (Settings Dialog Box)
      • File Menu
        • Create Signal Tap List File Command (File Menu)
          • Create Signal Tap File from Design Instance(s) Command (File Menu)
        • Print Options Dialog Box (Signal Tap Logic Analyzer)
      • Edit Menu
        • Find Bus Value Dialog Box
        • Plug-In Options Dialog Box
        • Create/Delete/Rename Instance Commands (Edit Menu)
        • Enable/Disable Power-up Trigger/Duplicate Trigger Commands (Edit Menu)
        • Bus Bit Order Commands (Edit Menu)
        • Bus Display Format Commands (Edit Menu)
        • Mnemonic Table Setup Dialog Box
          • Add Table Dialog Box
          • Add Entry Dialog Box
          • Import Table Dialog Box
        • Recreate State Machine Mnemonics Command (Edit Menu)
          • Recreate State Machine Mnemonics Dialog Box
        • Save to Data Log/Enable Data Log Commands (Edit Menu)
        • Use As Commands (Edit Menu)
        • Add State Machine Nodes Dialog Box
      • View Menu
        • Fit in Window/Zoom In/Zoom Out/Center on Trigger Commands (View Menu)
        • Instance Manager Pane (View Menu) (Signal Tap Logic Analyzer)
        • JTAG Chain Configuration Pane (View Menu) (Signal Tap Logic Analyzer)
        • Signal Configuration Pane (View Menu) (Signal Tap Logic Analyzer)
        • Hierarchy Display Pane (View Menu) (Signal Tap Logic Analyzer)
        • Data Log Pane (View Menu) (Signal Tap Logic Analyzer)
        • Delete All Time Bars/Next Transition/Previous Transition Commands (View Menu)
        • Insert Time Bar Dialog Box
        • Sample Numbers Command (View Menu)
        • Time Units Dialog Box
        • Delete All Time Bars/Next Transition/Previous Transition Commands (View Menu)
      • some other Menu
      • Analysis Commands (Processing Menu)
      • Setup Tab (Signal Tap Logic Analyzer)
        • Node List Pane (Signal Tap Logic Analyzer)
        • Insert Value Dialog Box
      • State-Based Trigger Flow Tab (Signal Tap Logic Analyzer)
      • Advanced Trigger Tab (Signal Tap Logic Analyzer)
        • Example of Using a Bitwise Object in an Advanced Trigger Condition
        • Examples of Constructing Advanced Trigger Conditions for the Signal Tap Logic Analyzer
        • Example of Using Data Delay in an Advanced Trigger Condition
        • Example of Using a Comparison Object and Pipelining in an Advanced Trigger Condition
        • Example of Using an Edge & Level Detector Object and Logical Conditions in an Advanced Trigger Condition
        • Example of Using a Shift Object in an Advanced Trigger Condition
        • Object Library Pane (Signal Tap Logic Analyzer)
      • Data Tab (Signal Tap Logic Analyzer)
        • Waveform Display Pane (Signal Tap Logic Analyzer)
          • Invert Signal Command (Shortcut Menu)
        • Master Time Bar Commands (Shortcut Menu)
      • SOF Manager Commands
      • Rename Command (Shortcut Menu) (Signal Tap Logic Analyzer)
      • State Diagram Pane (Signal Tap Logic Analyzer)
      • State Machine Pane (Signal Tap Logic Analyzer)
      • Resources Pane (Signal Tap Logic Analyzer)
      • Find Bus Value Commands
    • Debugging with the In-System Memory Content Editor
      • In-System Memory Content Editor Window
      • Export Data to File Dialog Box
      • Go To Dialog Box
      • Import Data from File Dialog Box
      • Instance Manager Pane
      • JTAG Chain Configuration Pane (View Menu) (In-System Memory Content Editor)
      • Read Information from In-System Memory Commands (Processing Menu)
      • Select Range Dialog Box
      • Stop In-System Memory Analysis Command (Processing Menu)
      • Custom Fill Dialog Box
      • Write Information to In-System Memory Commands (Processing Menu)
    • Debugging with the In-System Sources and Probes Editor
      • Instance Manager Pane
      • Select JTAG Debugging Information File Dialog Box
      • Set Alias/Delete Alias Commands (Edit Menu)
      • Bus Bit Order Commands (Edit Menu)
      • Bus Display Format Commands (Edit Menu)
      • Recreate Instances Commands (Edit Menu)
      • Set Value of Source Commands (Edit Menu)
      • JTAG Chain Configuration Pane (View Menu) (In-System Sources and Probes Editor)
      • Read Probe Data Commands (Processing Menu)
      • Source Data Commands (Processing Menu)
    • Debugging with the Logic Analyzer Interface
      • Logic Analyzer Interface Page (Settings Dialog Box)
    • System Console
      • System Console
      • Execute Script Dialog Box
      • About System Console Command
        • About System Console Window
      • GDB Server Control Panel (Tools Menu) (System Console)
      • Load Design (File Menu) (System Console)
      • Refresh Connections (Tools Menu) (System Console)
      • System Console Documentation Command
      • Specify Management Clock Dialog Box
    • Debugging with the Transceiver Toolkit
      • Transceiver Toolkit Window
      • Report Panel (Transceiver Toolkit)
      • Auto Sweep Panel (Receiver/Transceiver)
      • Control Channel and Control Link Panels
  • Optimizing Designs with the Design Space Explorer
    • Launch Design Space Explorer Command (Tools Menu)
  • Design Partition Planner
    • Design Partition Planner Commands
    • Bundle Configuration Dialog Box (Design Partition Planner)
    • Bundle Properties Dialog Box (Design Partition Planner)
    • Options Dialog Box (Design Partition Planner)
  • Power Estimation and Analysis
    • Power Analyzer Tool Window
    • Start Power Analyzer Command (Processing Menu)
    • Add/Edit Power Input File Dialog Box
    • Generate Early Power Estimator File Command (Project Menu)
    • HPS Power Calulator Dialog Box
    • Select Hierarchy Dialog Box
    • Power Analyzer Assignment Names
  • Analyzing Placed Resources with the Chip Planner
    • Chip Planner Options Dialog Box
    • Resource Property Editor Page (Options Dialog Box)
    • Tasks Window (Chip Planner)
    • Locate History Pane (Chip Planner)
    • Properties Tab (Chip Planner)
    • Report Window (Chip Planner)
    • Report Compilation Messages Dialog Box (Chip Planner)
    • Report HSSI Block Connectivity dialog box (Chip Planner)
    • Report Pins Dialog Box (Chip Planner)
    • Report Placed Pins By I/O Standard
    • Properties dialog box (Chip Planner)
    • Report Resources Dialog Box (Chip Planner)
    • Report Spine Clock Utilization dialog box (Chip Planner)
    • Report Used Clock Regions dialog box (Chip Planner)
    • Create Atom Dialog Box
    • Layers Settings Pane
    • Report Routing Utilization Dialog Box
  • Designing with Logic Lock Regions
    • Logic Lock Regions Window
    • Logic Lock Region Properties Dialog Box
      • Shapes tab
    • Region Filter Dialog Box
    • Rename Region Dialog Box
    • Understanding Logic Lock Region Assignments
  • Using the Netlist Viewer
    • Bird's Eye View Command (View Menu)
    • Hide Selection Commands (Shortcut Menu)
    • Filter Commands (Shortcut Menu)
    • Expand to Upper Hierarchy (Shortcut Menu)
    • Generate HDL File Command (Tools Menu)
    • Input Ports List/Ouput Ports List Commands (View Menu)
    • Properties Pane (Netlist Viewers)
    • RTL Viewer Command (Tools Menu)
    • Generate Other Files Dialog Box
    • Technology Map Viewer Command (Tools Menu)
    • Select Bus Index Dialog Box
    • Find Options Dialog Box (Netlist Viewers)
    • Find Pane (Netlist Viewers)
  • Devices and Adapters
    • Devices and Adapters
  • Logic Options
    • Advanced logic options
    • Global Signals logic options
    • Synchronize selections between tools
    • I/O Timing logic options
    • Synthesis logic options
    • Simulation logic options
    • Fitter Optimization
    • Others
    • All Logic Options
  • Intel® Quartus® Prime Scripting Support
    • About Intel® Quartus® Prime Scripting
  • Shortcuts
    • Keyboard Shortcuts and Toolbar Buttons
    • Generate Tcl File for Project Dialog Box
    • Tcl Scripts (Tools Menu)
  • Organize Intel® Quartus® Prime Settings File Command (Project Menu)
  • Examples of Assignment Syntax and Formatting in the Intel® Quartus® Prime Settings File
  • Tcl Console Command (View menu)
  • Glossary
    • Glossary
      • file types Definition
  • TCL Commands and Packages
  • List of Messages