Advanced HyperFlex Settings

The Advanced HyperFlex Settings control how Fast Forward Compilation analyzes and reports results for specific logical structures in the HyperFlex™ architecture of the Intel® Stratix® 10 FPGA. To access the settings, click Assignments > Settings > HyperFlex > Advanced Settings.
Table 1. Advanced HyperFlex Settings
Option Description
Fast Forward Compile Asynchronous Clears Specifies how Fast Forward analysis accounts for registers with asynchronous clear signals. The options are:
  • Auto—the Compiler assumes asynchronous clears are asynchronous until they limit timing performance during Fast Forward Compilation, at which point they are assumed removed
  • Preserve—the Compiler never assumes that it can remove or convert asynchronous clears for Fast Forward analysis.
Fast Forward Compile Fully Registered DSP Blocks Specifies how Fast Forward analysis accounts for DSP blocks that limit performance. Enable this option to generate results as if all DSP blocks are fully registered.
Fast Forward Compile Fully Registered RAM Blocks Specifies how Fast Forward analysis accounts for RAM blocks that limit performance. Enable this option to analyze the blocks as fully registered.
Fast Forward Compile Maximum Additional Pipeline Stages Specifies the maximum number of pipeline stages that Fast Forward compilation explores.
Fast Forward Compile User Preserve Directives Specifies how Fast Forward compilation accounts for restrictions from user-preserve directives.