Generate HDL (Generate Menu) (Platform Designer)

You open this dialog box in Platform Designer by clicking Generate > Generate HDL.

The Intel® Quartus® Prime software uses Platform Designer-generated synthesis HDL files during compilation. You can generate simulation HDL files, which can include simulation-only features targeted towards your simulator. You can generate simulation files as Verilog or VHDL, for use in your simulation environment. The Generation dialog box allows you to choose options to generate Platform Designer design files for synthesis and simulation.

Note: For more information about simulating a Platform Designer system, refer to "Simulating a Platform Designer System" in the Creating a System in Platform Designer chapter in volume 1 of the Intel® Quartus® Prime Handbook, and the Simulating Intel Designs chapter in volume 3 of the Intel® Quartus® Prime Handbook.