Power Analyzer Reports

Summarizes the following information about the power analysis performed, including the estimated total thermal power consumption of the design. The report also includes a confidence metric that reflects the overall quality of the data sources for the signal activities used in the power analysis.

• Power Analyzer Status shows the date and time that the Power Analyzer was last run, and indicates whether the power analysis completed successfully.
• Intel^® Quartus^® Prime Version shows the version of Intel^® Quartus^® Prime software in use.
• Revision Name shows the revision name of the design.
• Top-level Entity Name
• Family shows the name of the device family in use for the power analysis.
• Device shows the device number of the device in use for the power analysis.
• Power Models characterizes the power models in use for the power analysis.
• Total Thermal Power Dissipation shows the estimated total thermal power dissipation resulting for the design.
• Core Dynamic Thermal Power Dissipation shows the estimated core dynamic thermal power dissipation resulting for the design.
• Core Static Thermal Power Dissipation shows the estimated core static thermal power dissipation resulting for the design.
• I/O Thermal Power Dissipation shows the estimated I/O thermal power dissipation resulting for the design.
• Power Estimation Confidence characterizes the overall confidence in the signal activity data provided to the Power Analyzer. (See the Power Analyzer Confidence Metric report for details of the input data.)

Reports the settings used in the power analysis. These are as established on the Power Analyzer Settings and Operating Settings and Conditions pages. The report contains the following information:

• Default Power Toggle Rate specifies the power toggle rate in use.
• Default Power Input I/O Toggle Rate specifies the power input I/O toggle rate in use.
• Use Input File specifies the type of input file, if any, in use.
• Input Signal Activity File Name specifies the name of the Signal Activity File (.saf) Definition in use.
• Use smart compilation specifies whether smart compilation is turned on. This feature only supports the Intel^® Quartus^® Prime Standard Edition.
• Use vectorless estimation specifies whether vectorless estimation is turned on.
• Filter Glitches in VCD File Reader specifies whether glitch filtering is turned on.
• Power Analyzer Report Signal Activity specifies whether a signal activity section is created in the report.
• Power Analyzer Report Power Dissipation specifies whether a power dissipation section is created in the report
• Device Power Characteristics specifies the device power characteristics assumed for the power analysis.
• Automatically Compute Junction Temperature specifies whether junction temperature is computed.
• Specified Junction Temperature specifies a junction temperature.
• Ambient Temperature specifies the ambient temperature.
• Use Custom Cooling Solution specifies whether a custom cooling solution is in use.

Reports nodes that indicate an indeterminate toggle rate and lists the reason the node was reported.

Reports the output files, if any, produced by the Power Analyzer.

Lists the simulation files read, including the file ID, file name, file type, entity, VCD start time, VCD end time, the unknown %, and toggle %.

Reports the operating conditions used during power analysis performed using the Power Analyzer. This report appears only if your design targets a MAX^® II device family for compilation. The report contains the following information:

• Device power characteristics shows the device power characteristics as specified in the Operating Settings and Conditions page.
• Voltages shows the voltages used during power estimation.
• Auto computed junction temperature shows the user-entered or auto-computed temperatures used during power estimation.

• Board model used shows the model of board in the design if the device family supports board modeling.

Reports the total thermal power by block type, the block thermal dynamic power, the block thermal static power, and the routing thermal dynamic power for each block in the design.

Reports the total thermal power by block type, the block thermal dynamic power, the block thermal static power, the routing thermal dynamic power, and the block average toggle rate for each block in the design.

Reports the total thermal power by hierarchy, the block thermal dynamic power, the block thermal static power, the routing thermal dynamic power, and the full hierarchy name for each node in the design.

Reports the name of the clock domains, clock frequencies, and total core dynamic power for each clock domain.

Reports the total current drawn, the dynamic current drawn, and the static current drawn for each voltage supply in the design. For supported device families the report also lists the minimum specification power supply required for each voltage supply.

Reports the VCCIO voltage, the total current drawn, the dynamic current drawn, and the static current drawn for each I/O bank in the design.

Reports the total current drawn, the dynamic current drawn, the static current drawn, and the minimum power supply current for each VCCIO voltage in the design.

Reports the VCCPD voltage, the total current drawn, the dynamic current drawn, and the static current drawn for each I/O bank in the design.

Reports the total current drawn, the dynamic current drawn, the static current drawn, and the minimum power supply current for each VCCPD voltage in the design.

Reports the signal data sources and associated signal types the Power Analyzer uses when performing the power analysis. The following are possible data sources, listed in descending order of accuracy:

• User-entered assignment shows a node, entity, or clock assignment you assigned.
• Simulation data shows data in the form of a Signal Activity File (.saf) Definition or Value Change Dump File (.vcd) Definition file, generated by the Intel^® Quartus^® Prime Simulator or third-party simulator.
• User-specified input I/O default toggle rate shows the input I/O default toggle rate specified by the user on the Power Analyzer Settings page for input I/O, bidirectional, and virtual signals.
• Vectorless estimation shows signal activities derived by the Power Analyzer using probabilistic methods.
• Design-wide default values shows the default toggle rate you specified on the Power Analyzer Settings page for non-I/O, bidirectional, and virtual signals
• Assumed 0 shows instances where the user specified a default toggle rate as a percentage of the relevant clock rate. The Power Analyzer may occasionally be unable to identify the correct clock domain for the signal. A message is displayed because the toggle rate for the associated node is assumed to be zero.

The report lists the number of each of the above data sources used for each type of signal (pin, registered, and combinational), for both toggle rate and static probability data.

For data generated by a simulator (Signal Activity File (.saf) and Value Change Dump File (.vcd)), the summary also lists the percentage of nodes that toggled during the simulation, and the average percentage of time that nodes were in an unknown simulation state (a high-quality simulation is characterized by a high percentage of nodes in an unknown state for a lower percentage of simulation time).

Reports the toggle rates and static probabilities used by the Power Analyzer for all pins and signals with fan-out. For each signal, this report lists the signal type, the toggle rate, the data source for the toggle rate, the static probability, and the data source for the static probability.

Reports messages generated by the Power Analyzer during power analysis. The Power Analyzer generates info, warning, and error messages that report on conditions observed during the power analysis.

You can right-click a message in the Power Analyzer Messages report and click Help to display help on the selected message, or click Locate to view a list of options available for the selected message.