All Logic Options Add Pass-Through Logic to Inferred RAMs logic option Netlist Optimizations logic option Synchronization Register Chain Length logic option Alias logic option Shift Register Replacement - Allow Asynchronous Clear Signal logic option Allow Any RAM Size For Recognition logic option Allow Any ROM Size For Recognition logic option Allow Any Shift Register Size For Recognition logic option Allow Synchronous Control Signals logic option Auto Carry Chains logic option Auto Clock Enable Replacement logic option Auto Delay Chains logic option Auto DSP Block Replacement logic option Auto Global Clock logic option Auto Global Output Enable logic option Auto Global Register Control Signals logic option Auto Merge PLLs logic option Auto Open-Drain Pins logic option Auto RAM Block Balancing logic option Auto RAM Replacement logic option Auto Shift Register Replacement logic option Block Design Naming logic option Carry Chain Length logic option CKn/CK Pair logic option Current Strength logic option Disable Design Assistant Rule logic option Disable Register Merging logic option DQS Frequency logic option Input Delay from Dual-Purpose Clock Pin to Fan-out Destinations logic option Manual Logic Duplication logic option EDA Formal Verification Hierarchy logic option Enable Bus-Hold Circuitry logic option Enable Design Assistant Rule logic option Exclusive I/O Group logic option External Pin Connection logic option Extract Verilog State Machines logic option Extract VHDL State Machines logic option Final Placement Optimizations logic option Fitter Aggressive Routability Optimizations logic option Force Use of Synchronous Clear Signals logic option Global Signal logic option HDL Initial Fan-out Limit logic option HDL Message Level logic option Ignore CARRY Buffers logic option Ignore CASCADE Buffers logic option Ignore GLOBAL Buffers logic option Ignore LCELL Buffers logic option Ignore Maximum Fan-Out Assignments logic option Ignore ROW_GLOBAL Buffers logic option Ignore SOFT Buffers logic option Ignore translate_off and synthesis_off Directives logic option Ignore Verilog Initial Constructs logic option Implement as Clock Enable logic option Implement as Output of Logic Cell logic option Fast Input Register logic option I/O Placement Optimizations logic option I/O Standard logic option Logic Cell Insertion logic option Maximum Fan-Out logic option Maximum Number of M4K/M9K/M20K/M10K Memory Blocks logic option Enable Message logic option NOT Gate Push-Back logic option Number of Removed Registers Reported in Synthesis Report logic option Add to Simulation Output Waveforms logic option Optimize IOC Register Placement for Timing logic option Output Enable Group logic option Fast Output Enable Register logic option Fast Output Register logic option Automatic Asynchronous Signal Pipelining -- Allow Asynchronous Signal that Fans Out to Synchronous Inputs logic option Automatic Asynchronous Signal Pipelining Register Reach logic option Perform Register Retiming for Performance logic option Placement Effort Multiplier logic option PLL Compensation logic option PLL Ignore Migration Devices logic option Power Input File Settings logic option Power Analyzer Report Power Dissipation logic option Power Analyzer Report Signal Activity logic option Preserve PLL Counter Order logic option Programmable Differential Output Voltage (VOD) logic option Passive Resistor logic option Auto Packed Registers logic option Remove Redundant Logic Cells logic option Reserve Pin logic option Show Setup and Hold Time Violations logic option Add D and Q Ports of Register Node to Simulation Output Waveforms logic option Clock MUX Protection logic option Optimize Timing logic option I/O Maximum Toggle Rate logic option Treat Bidirectional Pin as Output Pin logic option Iteration limit for constant Verilog loops logic option Virtual Pin logic option Weak Pull-Up Resistor logic option Show "X" on Timing Violation logic option