Intel Quartus Prime Pro Edition User Guide: Partial Reconfiguration
Version Information
Updated for: |
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Intel® Quartus® Prime Design Suite 20.3 |
1. Creating a Partial Reconfiguration Design
The Intel® Quartus® Prime Pro Edition software supports the PR feature for the Intel® Stratix® 10, Intel® Agilex™ , Intel® Arria® 10, and Intel® Cyclone® 10 GX device families.
- Allows run-time design reconfiguration
- Increases scalability of the design through time-multiplexing
- Lowers cost and power consumption through efficient use of board space
- Supports dynamic time-multiplexing functions in the design
- Improves initial programming time through smaller bitstreams
- Reduces system down-time through line upgrades
- Enables easy system update by allowing remote hardware change
- A simplified compilation flow for partial reconfiguration
Hierarchical Partial Reconfiguration
Intel® Quartus® Prime Pro Edition software also supports hierarchical partial reconfiguration (HPR), with multiple parent and child design partitions, or multiple levels of partitions in a design. In HPR designs, a static region instantiates a parent PR region, and a parent PR region instantiates a child PR region. The same PR region reprogramming is possible for the child and parent partitions. Refer to Hierarchical Partial Reconfiguration.
Static Update Partial Reconfiguration
Static update partial reconfiguration (SUPR) allows you to define and modify a specialized static region, without requiring recompilation of all personas. This technique is useful for a portion of a design that you may possibly want to change for risk mitigation, but that never requires runtime reconfiguration. In PR without an SUPR partition, you must recompile all personas for any change to the static region. Refer to the Partial Reconfiguration Tutorials for detailed SUPR instructions.
Partial Reconfiguration Design Simulation
The Intel® Quartus® Prime Pro Edition software supports simulation of PR persona transitions through use of simulation multiplexers. You use the simulation multiplexers to change which persona drives logic inside the PR region during simulation. This simulation allows you to observe the resulting change and the intermediate effect in a reconfigurable partition. Refer to Partial Reconfiguration Design Simulation for details.
1.1. Partial Reconfiguration Terminology
This document refers to the following terms to explain partial reconfiguration:
Term | Description |
---|---|
Floorplan |
The layout of physical resources on the device. Creating a design floorplan, or floorplanning, is the process of mapping the logical design hierarchy to physical regions in the device. |
Hierarchical Partial Reconfiguration | Partial reconfiguration that includes multiple parent and child design partitions, or nesting of partitions in the same design. |
PR control block |
A dedicated block in Intel® Arria® 10 and Intel® Cyclone® 10 GX FPGAs. The PR control block processes the PR requests, handshake protocols, and verifies the cyclic redundancy check (CRC). |
PR host |
The system for coordinating PR. The PR host communicates with the PR control block ( Intel® Arria® 10 and Intel® Cyclone® 10 GX designs) or Secure Device Manager ( Intel® Stratix® 10 and Intel® Agilex™ designs). Implement the PR host within the FPGA (internal PR host) or in a chip or microprocessor. |
PR partition |
Design partition that you designate as Reconfigurable. A PR project can contain one or more PR partitions. |
PR Solutions Intel® FPGA IP |
Suite of Intel® FPGA IP that simplify implementation of PR handshaking and freeze logic, as Partial Reconfiguration Solutions IP User Guide describes. |
PR region |
A physical portion of FPGA device that you designate for partial reconfiguration. You define a PR region in the base configuration design. A device can contain more than one PR region. A PR region can be core-only, such as LAB, RAM, or DSP. The PR region bitstream configures this region. |
PR persona |
A specific PR partition implementation in a PR region. A PR region can contain multiple personas. Static regions contain only one persona. |
Revision |
A collection of settings and constraints for one version of your project. An Intel® Quartus® Prime Settings File (.qsf) preserves each revision of your project. Your Intel® Quartus® Prime project can contain several revisions. Revisions allow you to organize several versions of your design within a single project. |
Secure Device Manager (SDM) | A triple-redundant processor-based block in Intel® Agilex™ and Intel® Stratix® 10 devices that performs authentication, decryption, and decompression on the configuration data the block receives, before sending the data over to the configurable nodes through the configuration network. |
Snapshot |
The output of a Compiler stage. You can export the synthesis or final compilation results snapshot. |
Static region |
All areas not occupied by PR regions in your project. You associate the static region with the top-level partition of the design. The static region contains both the core and periphery locations of the device. The static region bitstream configures this region. |
Static update partial reconfiguration | A static region that allows change, without requiring the recompilation of all personas. This technique is useful for a portion of a design that you may possibly want to change for risk mitigation, but that never requires runtime reconfiguration. |
1.2. Partial Reconfiguration Process Sequence
- Send the stop_req signal to the PR region from the sequential PR control logic to prepare for the PR operation. Upon receiving this signal, the PR regions complete any pending transactions and stop accepting new transactions.
- Wait for the stop_ack signal to indicate that the PR region is ready for partial reconfiguration.
- Use PR control logic to freeze all necessary outputs of the PR regions. Additionally, drive the clock enable for any initialized RAMs to disabled state.
- Send the PR bitstream to the PR control block ( Intel® Arria® 10 and Intel® Cyclone® 10 GX designs) or SDM ( Intel® Stratix® 10 and Intel® Agilex™ designs) to initiate the PR process for the PR region. When using any of the Partial Reconfiguration Controller Intel® FPGA IP, the Avalon® memory-mapped or Avalon® streaming interface on the IP core provides this functionality. When directly instantiating the PR control block for Intel® Arria® 10 designs, refer to PR Control Block Signal Timing Diagrams
- On successful completion of the PR operation, reset the PR region.
- Signal the start of PR operation by asserting the start_req signal, and deasserting the freeze signal.
- Wait for the start_ack signal to indicate that the PR region is ready for operation.
- Resume operation of the FPGA with the newly reconfigured PR region.
1.3. Internal Host Partial Reconfiguration
In internal host control, an internal controller, a Nios® II processor, or an interface such as PCI Express* ( PCIe* ) or Ethernet, communicates directly with the Intel® Arria® 10 or Intel® Cyclone® 10 GX PR control block, or with the SDM in Intel® Stratix® 10 and Intel® Agilex™ devices.
When performing partial reconfiguration with an internal host, use the dedicated PR pins (PR_REQUEST, PR_READY, PR_DONE, and PR_ERROR) as regular I/Os. Implement your static region logic to retrieve the PR programming bitstreams from an external memory, for processing by the internal host.
Send the programming bitstreams for partial reconfiguration through the PCI Express* link. Then, you process the bitstreams with your PR control logic and send the bitstreams to the PR IP core for programming. nCONFIG moves the device out of the user mode into the device configuration mode.1
1.4. External Host Partial Reconfiguration
1.5. Partial Reconfiguration Design Flow
The PR design flow requires initial planning. This planning involves setting up one or more design partitions, and then determining the placement assignments in the floorplan. Well-planned PR partitions improve design area utilization and performance. The Intel® Quartus® Prime software also allows you to create nested PR regions as part of an HPR flow.
The PR design flow uses the project revisions feature in the Intel® Quartus® Prime software. Your initial design is the base revision, where you define the static region boundaries and reconfigurable regions on the FPGA. From the base revision, you create multiple revisions. These revisions contain the different implementations for the PR regions. However, all PR implementation revisions use the same top-level placement and routing results from the base revision.
The PR design flow includes the following steps:
- Step 1: Identify Partial Reconfiguration Resources
- Step 2: Create Design Partitions
- Step 3: Floorplan the Design
- Step 4: Add the Partial Reconfiguration Controller Intel FPGA IP
- Step 5: Define Personas
- Step 6: Create Revisions for Personas
- Step 7: Compile the Base Revision and Export the Static Region
- Step 8: Setup PR Implementation Revisions
- Step 9: Program the FPGA Device
1.5.1. Step 1: Identify Partial Reconfiguration Resources
All periphery resources, such as transceivers, external memory interfaces, GPIOs, I/O receivers, and hard processor system (HPS), must be in the static region. Partial reconfiguration of global network buffers for clocks and resets is not possible.
Hardware Resource Block | Reconfiguration Method |
---|---|
Logic Block | Partial reconfiguration |
Digital Signal Processing | Partial reconfiguration |
Memory Block | Partial reconfiguration |
Core Routing | Partial reconfiguration |
Transceivers/PLL | Dynamic reconfiguration |
I/O Blocks | Not supported |
Clock Control Blocks | Not supported |
After identifying the resources for PR, set up the design hierarchy and source code to support this partitioning. Refer to Partial Reconfiguration Design Considerations.
1.5.2. Step 2: Create Design Partitions
A design partition is only a logical partitioning of the design, and does not specify a physical area on the device. You associate a partition with a specific area of the FPGA using Logic Lock Region assignments. To avoid partitions obstructing design optimization, group the logic together within the same partition. If your design includes a hierarchical PR flow with parent and child partitions, you can define multiple parent or child partitions in your design, and multiple levels of PR partitions.
When you create a Reconfigurable partition, the Compiler preserves post-synthesis results for the partition and reuses the post-synthesis netlist, if you make no partition changes requiring re-synthesis. Otherwise, the Compiler resynthesizes the partition from source files. The Compiler adds wire LUTs for each interface of a Reconfigurable partition, and performs checks for PR compatibility. You must run elaboration before creating partitions.
Follow these steps to create design partitions:
- Click Processing > Start > Start Analysis & Elaboration.
- In the Project Navigator, right-click an instance in the Hierarchy tab, click Design Partition > Set as Design Partition. A design partition icon appears next to each partition you create.
- To view and edit all design partitions in the project, click Assignments > Design Partitions Window.
-
Specify Reconfigurable as the
partition Type for each PR partition. The
Reconfigurable type preserves synthesis results,
while allowing refit of the partition in the PR flow.
Figure 7. Design Partitions Window
1.5.3. Step 3: Floorplan the Design
Your PR region must include only core logic, such as LABs, RAMs, ROMs, and DSPs in a PR region. Intel® Agilex™ and Intel® Stratix® 10 designs can also include Hyper-Registers in the PR partition. Instantiate all periphery design elements, such as transceivers, external memory interfaces, and clock networks in the static region of the design. The Logic Lock regions you create can cross periphery locations, such as the I/O columns and the HPS, because the constraint is core-only.
- Place regions—use these regions to constrain logic to a specific area of the device. The Fitter places the logic in the region you specify. The Fitter can also place other logic in the region unless you designate the region as Reserved.
- Route regions—use these regions to constrain routing to a specific area. The routing region must fully enclose the placement region. Additionally, the routing regions for the PR regions cannot overlap.
Follow these guidelines when floorplanning your PR design:
- Complete the periphery and clock floorplan before core floorplanning. You can use Interface Planner (Tools > Interface Planner) to create periphery floorplan assignments for your design.
- Define a routing region that is at least 1 unit larger than the placement region in all directions.
- Do not overlap the routing regions of multiple PR regions.
- Select the PR region row-wise for least bitstream overhead. In Intel® Arria® 10 and Intel® Cyclone® 10 GX devices, short, wider regions generate smaller bitstreams than tall, narrower regions. Intel® Agilex™ and Intel® Stratix® 10 configuration occurs on sectors. For the least bitstream overhead, ensure that you align the PR region to sectors. Refer to "Analyzing and Optimizing the Design Floorplan," in Intel® Quartus® Prime Pro Edition User Guide: Design Optimization.
- For Intel® Arria® 10 and Intel® Cyclone® 10 GX devices, the height of your floorplan affects the reconfiguration time. A floorplan larger in the Y direction takes longer to reconfigure. This condition does not apply to Intel® Agilex™ or Intel® Stratix® 10 devices because they configure according to sectors.
- Define sub Logic Lock regions within PR regions to improve timing closure.
- If your design includes HPR parent and child partitions, the placement region of the parent region must fully enclose the routing and placement region of its child region. Also, the parent wire LUTs must be in an area outside the child PR region. This requirement is because the child PR region is exclusive to all other logic, which includes the parent and the static region.
1.5.3.1. Applying Floorplan Constraints Incrementally
- Implement the base revision using the most complex persona for each PR partition. This initial implementation must include the complete design with all periphery constraints, and top-level .sdc timing constraints. Do not include any Logic Lock region constraints for the PR regions with this implementation.
- Create partitions by setting the region Type option to Default in the Design Partitions Window, for all the PR partitions.
- Register the boundaries of each partition to ensure adequate timing margin.
- Verify successful timing closure using the Timing Analyzer.
- Ensure that all the desired signals are driven on global networks. Disable the Auto Global Clock option in the Fitter (Assignments > Settings > Compiler Settings > Advanced Settings (Fitter)), to avoid promoting non-global signals.
- Create Logic Lock core-only placement regions for each of the partitions.
- Recompile the base revision with the Logic Lock constraints, and then verify timing closure.
- Enable the Reserved option for each Logic Lock region to ensure the exclusive placement of the PR partitions within the placement regions. Enabling the Reserved option avoids placing the static region logic in the placement region of the PR partition.
- Recompile the base revision with the Reserved constraint, and then verify timing closure.
- In the Design Partitions Window, specify the Type for each of the PR partitions as Reconfigurable. This assignment ensures that the Compiler adds wire LUTs for each interface of the PR partition, and performs additional compilation checks for partial reconfiguration.
- Recompile the base revision with the Reconfigurable constraint, and then verify timing closure. You can now export the top-level partition for reuse in the PR implementation compilation of the different personas.
1.5.4. Step 4: Add the Partial Reconfiguration Controller Intel FPGA IP
1.5.4.1. Adding the Partial Reconfiguration Controller Intel FPGA IP
The Partial Reconfiguration Controller Intel FPGA IP interfaces with the Secure Device Manager (SDM) to manage the bitstream source. The SDM performs authentication and decompression on the configuration data. You can use this IP core in an Intel® Agilex™ or Intel® Stratix® 10 design when performing partial reconfiguration with an internal PR host, Nios® II processor, PCI Express* , or Ethernet interface.
The Intel® Quartus® Prime software supports PR over the core interface using the PR Controller IP core, or PR over the JTAG device pins. PR over JTAG pins does not require instantiation of the Partial Reconfiguration Controller Intel FPGA IP.
1.5.4.2. Adding the Partial Reconfiguration Controller Intel Arria 10/Cyclone 10 FPGA IP
Use this IP core in Intel® Arria® 10 or Intel® Cyclone® 10 GX designs when performing partial reconfiguration with an internal PR host, Nios® II processor, PCI Express* , or Ethernet interface.
During partial reconfiguration, you send a PR bitstream stored outside the FPGA to the PR control block inside the FPGA. This communication enables the control block to update the CRAM bits necessary for reconfiguring the PR region in the FPGA. The PR bitstream contains the instructions (opcodes) and the configuration bits necessary for reconfiguring a specific PR region.
Instantiate the IP core from the Intel® Quartus® Prime IP Catalog (Tools > IP Catalog) to automatically connect the IP to the Intel® Arria® 10 or Intel® Cyclone® 10 GX PR control block.
If you create your own custom logic to perform the function of the IP core, manually instantiate the control block to communicate with the FPGA system.
1.5.5. Step 5: Define Personas
Ensure that the signals interacting with the static region are a super-set of all the signals in all the personas. A PR design requires an identical I/O interface for each persona in the PR region. If all personas for your design do not have identical interfaces, you must also create wrapper logic to interface with the static region.
1.5.6. Step 6: Create Revisions for Personas
- Entity Rebinding assignment (ENTITY_REBINDING)—for each PR partition, the software adds an entity rebinding assignment with a place holder for the entity name. Your design may not require all of the entity rebinding assignments of each PR partition, based on the design and the implementation revision. For example, in HPR designs that use the default persona for the parent partition, you add the .qdb file for PR parent, and then use entity rebinding only for the child.
- QDB File Partition assignment (QDB_FILE_PARTITION)—the software adds this assignment for the static region, if you specify a .qdb file name.
- Revision Type Assignment (REVISION_TYPE)
- Click Project > Revisions.
- To create a new revision, double-click <<new revision>>.
- Specify a unique Revision name.
- Select an existing revision for the Based on revision option.
- For the Revision type, select Partial Reconfiguration - Base for the base revision or Partial Reconfiguration - Persona Implementation for an implementation revision.
-
Click Apply and OK.
Figure 11. Creating Revisions
The following assignments in the respective revision's .qsf file correspond to specifying the revision type from the Settings dialog box:
Base Revision Assignment:
set_global_assignment -name REVISION_TYPE PR_BASE
Implementation Revision Assignment:
set_global_assignment -name REVISION_TYPE PR_IMPL
For each PR partition, the Intel® Quartus® Prime software also adds the entity rebinding assignment to the .qsf:
set_instance_assignment -name ENTITY_REBINDING <entity_name> -to <hierarchical_path>
If you base a new implementation revision on an existing .qdb file, The Intel® Quartus® Prime software also adds the .qdb file partition assignment, with a place holder for the file name:
set_instance_assignment -name QDB_FILE_PARTITION <QDB file name>
As an example, to create a new implementation revision that uses a .qdb file from a base revision, use the following command:
create_revision impl_new -based_on <base_revision> \ -new_rev_type impl -root_partition_qdb_file base_static.qdb
- impl_new—specifies the name of a new implementation revision.
- -based_on <based_on_revision> — specifies the PR base revision that the new impl revision is based on. Some global assignments from the based_on revision are copied over to the impl revision. Placeholder entity rebinding assignments are created in the impl revision for each PR partition in the base.
- -new_rev_type <rev_type>— only useful rev-type is impl.
- root_partition_qdb_file <qdb_file>—creates a QDB_FILE_PARTITION assignment in impl revision with the specified .qdb file.
Figure 12. Partial Reconfiguration Compilation Flow
1.5.7. Step 7: Compile the Base Revision and Export the Static Region
- To specify the current revision, click Project > Revisions, and then set the base revision as current, or select the base revision from the main toolbar drop-down list.
-
For
Intel®
Arria® 10 and
Intel®
Cyclone® 10 GX designs, you can optionally add the following
assignments to the .qsf to automatically generate
the required PR bitstreams following compilation. This step is not required for
Intel®
Stratix® 10 or
Intel®
Agilex™
designs.
set_global_assignment -name GENERATE_PR_RBF_FILE ON set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
- To compile the base revision, click Processing > Start Compilation.
-
To export the static region, click Project > Export Design Partition and specify options for the partition export:
Figure 13. Export Design Partition
Table 3. Design Partition Options Option Setting Partition name Select root_partition. Partition database file Specify a descriptive file name. Include entity-bound SDC files Enable to include entity bound .sdc files with the partition export. Note: You must enable this option when exporting the base revision (roo partition), so that the implementation compiles inherit the timing constraints defined in entity-bound .sdc files.Snapshot Select final snapshot. -
Alternatively, follow these steps to automatically export one or more
design partitions after each compilation. You can automatically export any design
partition that does not have a preserved parent partition, including the
root_partition.
- To open the Design Partitions Window, click Assignments > Design Partitions Window.
- To automatically export a partition with synthesis results after any time you run synthesis, specify the a .qdb export path and file name for the Post Synthesis Export File option for that partition. If you specify only a file name without a path, the file exports to the project directory after compilation.
- To automatically export a partition with final snapshot results any time you run the Fitter, specify a .qdb file name for the Post Final Export File option for that partition.
Figure 14. Specifying Export File in Design Partitions WindowQSF File Equivalent:
set_instance_assignment -name \ EXPORT_PARTITION_SNAPSHOT_<FINAL|SYNTHESIZED> \ <hierarchy_path> -to <file_name>.qdb
1.5.8. Step 8: Setup PR Implementation Revisions
- Set an implementation revision as the Current Revision.
- To specify the .qdb file as the source for root_partition, click Assignments > Design Partitions Window. Double-click the Partition Database File cell and specify the appropriate .qdb file.
-
For each PR implementation revision, specify the name of the
entity that you want to partially reconfigure in the Entity Re-binding cell. This entity name comes from the design
file for the persona you want to implement in this implementation
revision.
Figure 15. Design Partitions Window
- To compile the design, click Processing > Start Compilation.
-
Repeat steps 1 through 4 to setup and compile each
implementation revision. Alternatively, use a simple Tcl script to compile all
implementation revisions:
set_current_revision <implementation1 revision name> execute_flow -compile set_current_revision <implementation2 revision name> execut_flow -compile . . .
Note: When you generate a static .qdb for import into a PR implementation compile, make sure to preserve the entity-bound .sdc files for the static partition. Also, for the implementation revision to properly process the .sdc files, the order of assignments in the implementation file .qsf is very important. Verify the order of the .sdc files in the implementation revision. The implementation revision includes the entity-bound .sdc constraints pulled in by the static region .qdb. The implementation revision also includes the .sdc files for the implementation revision. If you require the .sdc files pulled in by the static region .qdb before the implementation revision .sdc files, ensure that the QDB_FILE_PARITION assignment appears before any other .sdc file assignment.
1.5.9. Step 9: Program the FPGA Device
For Intel® Stratix® 10 and Intel® Agilex™ designs, the Assembler generates a configuration .rbf automatically at the end of compilation. For Intel® Arria® 10 and Intel® Cyclone® 10 GX designs, you can add the GENERATE_PR_RBF_FILE assignment to the .qsf or use the Convert Programming Files dialog box to convert the Partial-Masked SRAM Object Files (.pmsf) to an .rbf file, as Generating PR Bitstream Files describes.
Programming File | Description |
---|---|
<rev>.<pr_region>.pmsf | Contains the partial-mask bits for the PR region.
The .pmsf file contains all the
information for creating PR bitstreams. Note: The default file name corresponds to the
partition name.
|
<rev>.<static_region>.msf | Contains the mask bits for the static region. |
<rev>.sof | Contains configuration information for the entire device. |
1.5.9.1. Generating PR Bitstream Files
Generating PR Bitstreams During Compilation
Follow these steps to generate the .rbf file during compilation:
- Add the following assignments to the revision .qsf
to automatically generate the required PR bitstreams following
compilation:
set_global_assignment -name GENERATE_PR_RBF_FILE ON set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
- To compile the revision and generate the .rbf, click Processing > Start Compilation.
Generating PR Bitstreams with Programming File Generator
Follow these steps to generate the .rbf for PR programming with the Programming File Generator:
- Click File > Programming File Generator. The Programming File Generator appears.
- Specify the target Device family and the Configuration mode for partial reconfiguration.
- On the Output File tab, specify the Output directory, file name, and enable the Raw Binary File for Partial Reconfiguration (.rbf) file type.
- To add the input .pmsf file to
convert, click the Input Files tab, click
Add Bitstream, and specify the .pmsf that you generated in the Assembler.Figure 16. Adding Bitstream File
- On the Input Files tab, select the bitstream
.pmsf file and click
Properties. Specify any of the following options for the
.rbf:
- Enable compression—generates compressed PR bitstream files to reduce file size.
- Enable encryption—generates encrypted independent bitstreams for base image and PR image. You can encrypt the PR image even if your base image has no encryption. The PR image can have a separate encryption key file (.ekp). You can also specify other Security settings.
- If you turn on Enable encryption, you must
also acknowledge the Design Security Feature Disclaimer by
checking the box.Figure 17. Design Security Feature Disclaimer
- Click OK.
- In Programming File Generator, click Generate. The PR bitstream files generate according to your specifications.
Generating PR Bitstreams with Convert Programming Files Dialog Box
Follow these steps to generate the .rbf with the Convert Programming Files dialog box:
- Click File > Convert Programming Files. The Convert Programming Files dialog box appears.
- Specify the output file name and Programming file type as Raw Binary File for Partial Reconfiguration (.rbf).
- To add the input .pmsf file to convert, click Add File.
- Select the newly added .pmsf file, and click Properties.
- Enable or disable any of the following options and click OK:
- Compression—enables compression on PR bitstream.
- Enhanced compression—enables enhanced compression on PR bitstream.
- Generate encrypted bitstream—generates encrypted independent bitstreams for base image and PR image. You can encrypt the PR image even if your base image has no encryption. The PR image can have a separate encryption key file (.ekp). If you enable Generate encrypted bitstream, enable or disable the Enable volatile security key, Use encryption lock file, and Generate key programming file options.
- Click Generate. The PR bitstream files generate according to your specifications.
1.5.9.2. Partial Reconfiguration Bitstream Compatibility Checking
Intel® Stratix® 10 and Intel® Agilex™ PR Bitstream Compatibility Checking
For Intel® Stratix® 10 and Intel® Agilex™ designs, PR bitstream compatibility checking is automatically enabled in the Compiler and in the Secure Device Manager (SDM) firmware by default. The following limitations apply to PR designs if PR bitstream compatibility checking is enabled:
- The firmware allows up to a total of 32 PR regions, irrespective of the number of hierarchical partial reconfiguration layers.
- Your PR design can have up to six hierarchical partial reconfiguration layers.
- Your PR design, when there is no hierarchy, can have up to 32 regions.
- Your PR design can have up to 15 child PR regions of any parent PR region (if it is hierarchical). Child PR regions count towards the total limit of 32 PR regions.
The Compiler generates an error if your PR design exceeds these limits when PR bitstream compatibility checking is enabled.
set_global_assignment -name ENABLE_PR_POF_ID OFFWhen you set this assignment to off, the limit of 32 total regions does not apply in the Compiler.
Intel® Arria® 10 and Intel® Cyclone® 10 GX PR Bitstream Compatibility Checking
For Intel® Arria® 10 and Intel® Cyclone® 10 GX designs, you enable or disable PR bitstream compatibility checking by turning on the Enable bitstream compatibility check option when instantiating the Partial Reconfiguration Controller Intel® Arria® 10 /Cyclone 10 FPGA IP from the IP Catalog.
The PR IP verifies the partial reconfiguration PR Bitstream file (.rbf). When you enable the bitstream compatibility check, the PR .pof ID is encoded as the 71st word of the PR bitstream. If the PR IP detects an incompatible bitstream, then the PR IP stops the PR operation, and the status output reports an error.
When you turn on Enable bitstream compatibility check, the PR Controller IP core creates a PR bitstream ID and displays the bitstream ID in the configuration dialog box. For bitstream compatibility checking with hierarchical PR designs, refer to additional steps in AN 806: Hierarchical Partial Reconfiguration Tutorial for Intel® Arria® 10 GX FPGA Development Board.
1.5.9.3. Raw Binary Programming File Byte Sequence Transmission Examples
Double Word = 01EE1B02 | |||
LSB: BYTE0 = 02 | BYTE1 = 1B | BYTE2 = EE | MSB: BYTE3 = 01 |
D[7..0] | D[15..8] | D[23..16] | D[31..24] |
0000 0010 | 0001 1011 | 1110 1110 | 0000 0001 |
1.5.9.4. Generating a Merged .pmsf File from Multiple .pmsf Files
Use a single merged .rbf file to reconfigure two PR regions simultaneously. To merge two or more .pmsf files:
- Open the Convert Programming Files dialog box.
- Specify the output file name and programming file type as Merged Partial-Mask SRAM Object File (.pmsf).
- In the Input files to convert dialog box, select PMSF Data.
- To add input files, click Add File. You must specify two or more files for merging.
- To generate the merged file, click Generate.
Alternatively, to merge two or more .pmsf files from the Intel® Quartus® Prime shell, type the following command:
quartus_cpf --merge_pmsf=<number of merged files> <pmsf_input_file_1> \ <pmsf_input_file_2> <pmsf_input_file_etc> <pmsf_output_file>
For example, to merge two .pmsf files, type the following command:
quartus_cpf --merge_pmsf=<2> <pmsf_input_file_1> <pmsf_input_file_2> \ <pmsf_output_file>
1.6. Partial Reconfiguration Design Considerations
For example, during PR programming, you must ensure that other parts of the system do not read or write to the PR region. You must also freeze the write enable output from the PR region into the static region, to avoid interference with static region operation. If all personas for your design do not have identical top-level interfaces, you must create the wrapper logic to ensure that all the personas appear similar to the static region. Upon partial reconfiguration of a PR region, you must bring the registers in the PR region to a known state by applying a reset sequence. There are specific guidelines for global signals and on-chip memories. The following sections provide design considerations and guidelines to help you create design files for a PR design.
FPGA Device and Software Considerations
- Only Intel® Arria® 10 and Intel® Cyclone® 10 GX devices in -1, -2 and -3 speed grade support partial reconfiguration. All Intel® Agilex™ and Intel® Stratix® 10 devices support PR.
- Use the nominal VCC of 0.9V or 0.95V as per the datasheet, including VID enabled devices.
- To minimize Intel® Arria® 10 and Intel® Cyclone® 10 GX programming files size, ensure that the PR regions are short and wide. For Intel® Agilex™ and Intel® Stratix® 10 designs, use sector-aligned PR regions.
- The Intel® Quartus® Prime Standard Edition software does not support partial reconfiguration for Intel® Arria® 10 devices, nor provide any support for Intel® Agilex™ nor Intel® Stratix® 10 devices.
- The current version of the Intel® Quartus® Prime Pro Edition software supports only one Signal Tap File (.stp) per revision.
Design Partition Considerations
- Reconfigurable partitions can only contain core resources, such as LABs, RAMs, and DSPs. All periphery resources, such as the transceivers, external memory interface, HPS, and clocks must be in the static portion of the design.
- To physically partition the device between static and individual PR regions, floorplan each PR region into exclusive, core-only, placement regions, with associated routing regions.
- A reconfiguration partition must contain the super-set of all ports that you use across all PR personas.
Clocking, Reset, and Freeze Signal Considerations
- The maximum number of clocks or other global signals for any Intel® Arria® 10 or Intel® Cyclone® 10 GX PR region is 33. The maximum number of clocks or other global signals for any Intel® Agilex™ or Intel® Stratix® 10 PR region is 32. In the current version of the Intel® Quartus® Prime Pro Edition software, no two PR regions can share a row-clock.
- PR regions do not require any input freeze logic. However, you must freeze all the outputs of each PR region to a known constant value to avoid unknown data during partial reconfiguration.
- Increase the reset length by 1 cycle to account for register duplication in the Fitter.
- Ensure that all low-skew global signals (clocks and resets) driving into PR region in base revision compilations have destinations.
1.6.1. Partial Reconfiguration Design Guidelines
The following table lists important design guidelines at various steps in the PR design flow:
PR Design Step | Guideline | Reason |
---|---|---|
Designing for partial reconfiguration |
Do not assume initial states in registers inside PR region. After PR is complete, ensure that you reset all the control path registers to a known state, but omit the data path registers. |
Registers inside the PR region contain undefined values after reconfiguration. Omitting data path registers reduces congestion on reset signals. |
You cannot define synchronous reset as a global signal for Intel® Arria® 10 or Intel® Cyclone® 10 GX partial reconfiguration. |
PR regions do not support synchronous reset of registers as a global signal, because the Intel® Arria® 10 and Intel® Cyclone® 10 GX LAB does not support synchronous clear (sclr) signal on a global buffer. The LAB supports the asynchronous clear (aclr) signal driven from a local input, or from a global network row clock. As a result, only the aclr can be a global signal, feeding registers in a PR region. |
|
The PRESERVE_FANOUT_FREE_NODE assignment cannot preserve a fanout-free register that has no fanout inside the Verilog HDL or VHDL module in which you define it. To preserve these fanout-free registers, implement the noprune pragma in the source file: (*noprune*)reg r; If there are multiple instances of this module, with only some instances requiring preservation of the fanout-free register, set a dummy pragma on the register in the HDL and also set the PRESERVE_FANOUT_FREE_NODE assignment. This dummy pragma allows the register synthesis to implement the assignment. For example, set the following dummy pragma for a register r in Verilog HDL: (*dummy*)reg r; Then set this instance assignment: set_instance_assignment -name \ PRESERVE_FANOUT_FREE_NODE ON \ -to r; |
The PRESERVE_FANOUT_FREE_NODE assignment does not apply when a register is not used in the Verilog HDL or VHDL module in which it is defined. | |
Partitioning the design |
Register all the inputs and outputs for your PR region. |
Improves timing closure and time budgeting. |
Reduce the number of signals interfacing the PR region with the static region in your design. |
Reduces the wire LUT count. |
|
Create a wrapper for your PR region. |
The wrapper creates common footprint to static region. |
|
Drive all the PR region output ports to inactive state when the PR region is held in reset and the freeze bit is asserted for the PR region. |
Prevents the static region logic from receiving random data during the partial reconfiguration operation. |
|
PR boundary I/O interface must be a superset of all the PR persona I/O interfaces. |
Ensures that each PR partition implements the same ports. |
|
Preparing for partial reconfiguration |
Complete all pending transactions. |
Ensures that the static region is not in a wait state. |
Maintaining a partially working system during partial reconfiguration |
Hold all outputs to known constant values. |
Ensures that the undefined values the PR region receives during and after the reconfiguration do not affect the PR control logic. |
Initializing after partial reconfiguration |
Initialize after reset. |
Retrieves state from memory or other device resources. |
Debugging the design using Signal Tap Logic Analyzer |
|
The current version of the Intel® Quartus® Prime software supports only one .stp (Signal Tap file) per revision. This limitation requires you to select partitions, one at a time, to tap. |
Do not tap across regions in the same .stp file. |
Ensures consistent interface (boundary) across all personas. |
|
Tap only the pre-synthesis signals. In the Node Finder, filter for Signal Tap: pre-synthesis. |
Ensures that the signal tapping of PR personas start from synthesis. |
1.6.2. PR Design Timing Closure Best Practices
The use of partition boundary ports for PR regions can make timing closure more challenging because the Compiler cannot optimize the logic across a partition boundary. The use of Logic Lock regions can also limit placement and routing flexibility. You must register all PR region boundary ports. Even when taking these steps, you may still find timing criticalities.
Each persona of a PR region can have different bits or input and output buses in use. Therefore, it is important to preserve the registers that do not have fan-out in a given persona, or that are driven by constants. You must ensure that the Compiler does not optimize away such registers during the compilation of a persona.
If the base compile does not use some bits of a bus, and the Compiler removes the corresponding registers for those bits, the logic may be untimed, resulting in unfavorable placement and routing. If you use those unregistered paths in other persona logic, you can have difficulty meeting timing on those paths. Preserving the unused port registers in the base compile ensures that the paths are timed in the base compile, and eases timing closure during persona compiles.
Follow these guidelines for effective register preservation in PR designs:
- Only the registers within PR regions require preservation.
- Only the PR base compilation requires register preservation.
- In a persona compile, the Compiler can safely remove fan-out free and constant-driven registers.
- For hierarchical PR compilations, only the base compile of the hierarchy requires register preservation.
- Preserve fan-out free nodes for input registers.
- Preserve constant-driven nodes for output registers.
- Only assign the attributes for the PR base compile. Remove the attributes for the persona compile (for example, via parameter or generic).
- You can set top-level parameters in the .qsf, which in turn pass down to lower hierarchies.
Use any of the following synthesis attributes to preserve registers:
- To preserve constant-driven or fan-out free registers, use the noprune attribute. noprune also
disables all physical
optimizations:
Verilog: (* noprune *) reg reg1; VHDL: signal reg1: std_logic; attribute noprune: boolean; attribute noprune of reg1: signal is true;
- To preserve fan-out free registers while allowing retiming on bits that
have fan-outs, assign PRESERVE_FANOUT_FREE_NODE ON as
altera_attribute:
Verilog: (* altera_attribute = "-name PRESERVE_FANOUT_FREE_NODE ON" *) \ reg reg1; VHDL: signal reg1: stdlogic; attribute altera_attribute : string; attribute altera_attribute of reg1: signal is "-name PRESERVE_FANOUT_FREE_NODE ON";
- Alternatively, use the dummy attribute
with the PRESERVE_FANOUT_FREE_NODE ON assignment in the
.qsf:
Verilog: (* dummy *) reg reg1; VHDL: signal reg1: std_logic; attribute dummy: boolean; attribute dummy of reg1: signal is true;
.qsf Assignment:
set_instance_assignment -name PRESERVE_FANOUT_FREE_NODE ON \ -to <hierarchical path to reg1>
- To preserve constant-driven registers while allowing retiming on bits
that have drivers, use the preserve_syn_only
attribute:
Verilog: (* preserve_syn_only *) reg reg1; VHDL: signal reg1: std_logic; attribute preserve_syn_only : boolean; attribute preserve_syn_only of reg1: signal is true;
The following example shows how to assign attributes in PR base compile using a parameter in System Verilog and in VHDL. The example contains a parameter called base_compile, which is set to true for the PR base compile only.
System Verilog: localparam ON_OFF_STRING = base_compile ? "ON": "OFF"; (* altera_attribute = {"-name PRESERVE_FANOUT_FREE_NODE ", ON_OFF_STRING} *) logic [WIDTH-1:0] pr_input_register; (* altera_attribute = {"-name PRESERVE_REGISTER_SYN_ONLY ", ON_OFF_STRING} *) logic [WIDTH-1:0] pr_output_regsiter; VHDL: attribute altera_attribute : string; type attributeStr_type is array(boolean) of string(1 to 35); constant attributeStr : attributeStr_type := (true => "-name PRESERVE_FANOUT_FREE_NODE ON \ ", false => "-name PRESERVE_FANOUT_FREE_NODE OFF"); attribute altera_attribute of <PR input registers> : signal is attributeStr(base_compile); attribute preserve_syn_only : boolean; attribute preserve_syn_only of <PR output registers> : signal is base_compile;
1.6.3. PR File Management
Method 1 (Preferred): Specify Unique Entity and File Names for Each Persona
To illustrate these methods, consider a design that includes two PR regions, each with the possible apple, orange, and banana personas.In PR file management method 1, you specify unique entity and file name pairs for each persona in the project. For example:
- Define the apple persona in the apple.sv file
- Define the orange persona in the orange.sv file
- Define the banana persona in the banana.sv file
In the base PR revision RTL, you specify "apple" as the PR persona for both PR regions:
When you set the base persona to [apple, apple] by setting u_fruit_0 and u_fruit_1 as the PR partition and regions, you can easily change the persona occupying the PR region using the Entity Rebinding (ENTITY_REBINDING) option in the Design Partitions Window, or by editing the .qsf directly, as the following examples show:
To specify the orange persona for the PR implementation (impl) revision:
set_instance_assignment -name ENTITY_REBINDING orange -to u_fruit_0 set_instance_assignment -name ENTITY_REBINDING orange -to u_fruit_1
To specify the banana persona for the PR implementation (impl) revision:
set_instance_assignment -name ENTITY_REBINDING banana -to u_fruit_0 set_instance_assignment -name ENTITY_REBINDING banana -to u_fruit_1
To specify the different personas for each PR region:
set_instance_assignment -name ENTITY_REBINDING orange -to u_fruit_0 set_instance_assignment -name ENTITY_REBINDING banana -to u_fruit_1
For each implementation revision, you must ensure that you include the corresponding source file in the project (Project > Add/Remove Files in Project).
Method 2: Parametrize a Single File as PR Persona
In PR file management method 2, you use a wrapper file and parameters to parameterize a single file that defines all personas. For example, consider the same design that method 1 describes with two PR regions, each with three possible personas for each PR region.
In the following example, u_fruit_0 and u_fruit_1 are set as the PR partitions and regions in the base compile. The FRUIT_TYPE parameter of 0 generates the apple entity for both PR personas.
You can then change the parameter values to change the personas. For example, to specify the orange persona for both PR regions, set the FRUIT_TYPE parameter to 1: (FRUIT_TYPE=1)
In addition to these changes to RTL, you must also follow these additional steps when using method 2 to update the .qsf:
- Create a copy of your fruit.sv file. Name the file with a unique name, such as x_fruit.sv. Also rename the entity to match the .sv file.
- Set the default parameter of FRUIT_TYPE to
a Verilog macro, in this case, `X_FRUIT_TYPE.Figure 23. Copy of fruit.sv Saved as x_fruit.sv
- Add x_fruit.sv to the project (Project > Add/Remove Files in Project).
- Specify the following in the PR implementation revision's
.qsf file:
- Add the following line to set the `X_FRUIT_TYPE Verilog macro to 1, and to specify the proper parameter for "fruit" that
instantiates the correct FRUIT_TYPE:
set_global_assignment -name VERILOG_MACRO "X_FRUIT_TYPE=1"
- Specify the entity rebinding assignment to associate the new x_fruit entity with instances of u_fruit_0 and u_fruit_1:
set_instance_assignment -name ENTITY_REBINDING x_fruit -to u_fruit_0 set_instance_assignment -name ENTITY_REBINDING x_fruit -to u_fruit_1
These .qsf changes set orange as the new persona for both PR regions.
- Add the following line to set the `X_FRUIT_TYPE Verilog macro to 1, and to specify the proper parameter for "fruit" that
instantiates the correct FRUIT_TYPE:
- One downside of method 2 is that the Verilog macro set in the .qsf file is global. Therefore, every instance of
`X_FRUIT_TYPE in the project defaults to a
value of 1. This result may be suitable if you
want both PR personas to be of the same type. However, if you want to specify
“orange” for one persona and “banana” for another persona in one PR
implementation compile, you must create another copy of the fruit.sv file with a unique name and Verilog
macro:Figure 24. Copy of x_fruit.sv Saved as y_fruit.sv
- Specify the following in the PR implementation revision's
.qsf file:
- Add the following line to set the `X_FRUIT_TYPE Verilog macro to 1, and to specify the proper parameter for "fruit" that
instantiates the correct FRUIT_TYPE:
set_global_assignment -name VERILOG_MACRO "X_FRUIT_TYPE=1" set_global_assignment -name VERILOG_MACRO "Y_FRUIT_TYPE=2"
- Specify the entity rebinding assignment to associate the new x_fruit entity with instances of u_fruit_0 and the new y_fruit entity with u_fruit_1:
set_instance_assignment -name ENTITY_REBINDING x_fruit -to u_fruit_0 set_instance_assignment -name ENTITY_REBINDING y_fruit -to u_fruit_1
These .qsf changes specify orange as the persona for the first PR region, and banana as the persona for the second PR region.
- Add the following line to set the `X_FRUIT_TYPE Verilog macro to 1, and to specify the proper parameter for "fruit" that
instantiates the correct FRUIT_TYPE:
1.6.4. Evaluating PR Region Initial Conditions
After compiling the base revision that defines the partition, you can view the Registers with Explicit Power-Up Settings report for the partition to identify, locate, and correct any unintended initial conditions. For a specific PR partition, you can view the power-up initial values after synthesizing the base revision in the Synthesis report. The Synthesis report includes power-up initial values in the Partition Statistics section.
The Messages window also generates a warning or error message about any initial conditions during synthesis processing. After evaluating the initial condition, you can determine whether the condition is correct for design functionality, or change the design to remove dependence on an initial condition that is incompatible with partial reconfiguration.
1.6.5. Creating Wrapper Logic for PR Regions
During the PR compilation, the Compiler converts each of the non-global ports on interfaces of the PR region into boundary port wire LUTS. The naming convention for boundary port wire LUTs are <input_port>~IPORT for input ports, and <output_port>~OPORT for output ports. For example, the instance name of the wire LUT for an input port with the name my_input, on a PR region with the name my_region, is my_region|my_input~IPORT.
- Manually floorplan the boundary ports using Logic Lock region assignments, or place the boundary ports automatically using the Fitter. The Fitter places the boundary ports during the base revision compile. The boundary LUTs are invariant locations the Fitter derives from the persona you compile. These LUTs represent the boundaries between the static region and the PR routing and logic. The placement remains stationary regardless of the underlying persona, because the routing from the static logic does not vary with a different persona implementation.
-
To constrain all boundary ports within a given region, use a wildcard
assignment. For example:
set_instance_assignment -name PLACE_REGION "65 59 65 85" -to \ u_my_top|design_inst|pr_inst|pr_inputs.data_in*~IPORT
This assignment constrains all the wire LUTS corresponding to the IPORTS that you specify within the place region, between the coordinates (65 59) and (65 85).
Figure 26. Wire-LUTs at the PR Region BoundaryOptionally, floorplan the boundary ports down to the LAB level, or individual LUT level. To floorplan to the LAB level, create a 1x1 Logic Lock PLACE_REGION constraint (single LAB tall and a single LAB wide). Optionally, specify a range constraint by creating a Logic Lock placement region that spans the range. For more information about floorplan assignments, refer to Floorplan the Partial Reconfiguration Design.
1.6.6. Creating Freeze Logic for PR Regions
The PR region cannot drive valid data until the partial reconfiguration process is complete, and the PR region is reset. Freezing is important for control signals that you drive from the PR region.
The freeze technique that you choose is optional, depending on the particular characteristics of your design. The freeze logic must reside in the static region of your design. A common freeze technique is to instantiate 2-to-1 multiplexers on each output of the PR region, to hold the output constant during partial reconfiguration.
An alternative freeze technique is to register all outputs of the PR region in the static region. Then, use an enable signal to hold the output of these registers constant during partial reconfiguration.
The Partial Reconfiguration Region Controller IP core includes a freeze port for the region that it controls. Include this IP component with your system-level control logic to freeze the PR region output. For designs with multiple PR regions, instantiate one PR Region Controller IP core for each PR region in the design. The Intel® Quartus® Prime software includes the Avalon® Memory-Mapped Freeze Bridge and Avalon® Streaming Freeze Bridge Intel® FPGA IP cores. You can use these IP cores to implement freeze logic, or design your own freeze logic for these standard interface types.
The static region logic must be independent of all the outputs from the PR regions for a continuous operation. Control the outputs of the PR regions by adding the appropriate freeze logic for your design.
1.6.7. Resetting the PR Region Registers
PR Reset Type | Active-High Synchronous Reset | Active-High Asynchronous Reset | Active-Low Synchronous Reset | Active-Low Asynchronous Reset |
---|---|---|---|---|
On local signal |
Yes | Yes | Yes | Yes |
On global signal |
|
Yes |
|
Yes |
1.6.8. Promoting Global Signals in a PR Region
In PR designs, the Compiler disables global promotion for signals originating within the logic of a PR region. Instantiate the clock control blocks only in the static region, because the clock floorplan and the clock buffers must be a part of the static region of the design. Manually instantiating a clock control block in a PR region, or assigning a signal in a PR region with the GLOBAL_SIGNAL assignment, results in compilation error. To drive a signal originating from the PR region onto a global network:
- Expose the signal from the PR region.
- Drive the signal onto the global network from the static region.
- Drive the signal back into the PR region.
You can drive a maximum of 33 clocks (for Intel® Arria® 10 and Intel® Cyclone® 10 GX devices), or 32 clocks (for Intel® Agilex™ and Intel® Stratix® 10 devices) into any PR region. You cannot share a row clock between two PR regions.
The Compiler allows only certain signals to be global inside a PR region. Use only global signals to route secondary signals into a PR region, as the following table describes:
Block Type | Supported Global Network Signals |
---|---|
LAB, MLAB | Clock, ACLR, SCLR3 |
RAM, ROM (M20K) | Clock, ACLR, Write Enable (WE), Read Enable (RE), SCLR |
DSP | Clock, ACLR, SCLR |
1.6.8.1. Viewing Row Clock Region Boundaries
-
Right-click a PR partition name in the Design Partitions Window and click
Locate Node > Locate in Chip Planner.
Figure 29. Row Clock Region Boundaries in Chip Planner
- In Chip Planner, click the Layers tab and select the Basic layer. The Chip Planner overlays the row clock region boundaries. Adjust the Basic layer settings to display specific items.
1.6.9. Planning Clocks and other Global Routing
During the base revision compile, you must route any global signal that any PR persona requires into a destination in the PR region. For clocks signals, this destination is a register or other synchronous element and the signal entering the clock input. For a reset, the destination should be fed into the appropriate input.
This requirement occurs because PR only reconfigures the last part of the low skew network. If you do not route the root and middle sections of the network during the base compile, you cannot use that revision for the PR.
Consider an example with a super-set of signals for a PR region that consists of:
- Three clocks—clk_1, clk_2, and clk_3.
- Two resets—rst_1 and rst_2.
- Base PR persona—uses clk_1, clk_2, and rst_1 only.
- Other personas—use clk_3 and rst_2 only.
In this example, the base persona must have a proper destination for the "unused" clk_3 and rst_2. You can accomplish this by driving a single register with a (*no prune*) directive inside the base PR persona, with clk_3 and reset using rst_2.
Omitting these destinations results in an error during compilation of the PR implementation second persona.
1.6.10. Implementing Clock Enable for On-Chip Memories with Initialized Contents
- To avoid spurious writes during PR programming for memories with initialized contents, implement the clock enable circuit in the same PR region as the M20K or MLAB RAM. This circuit depends on an active-high clear signal from the static region.
- Before you begin the PR programming, assert this signal to disable the memory’s clock enable. Your system PR controller must deassert the clear signal on PR programming completion. You can use the freeze signal for this purpose.
- Use the Intel® Quartus® Prime IP Catalog or Platform Designer to instantiate the On-Chip Memory and RAM Intel® FPGA IP cores that include an option to automatically add this circuitry.
Verilog RTL for Clock Enable
reg ce_reg; reg [1:0] ce_delay; always @(posedge clock, posedge freeze) begin if (freeze) begin ce_delay <= 2'b0; end else begin ce_delay <= {ce_delay[0], 1'b1}; end end always @(posedge clock, negedge ce_delay[1]) begin if (~ce_delay[1]) begin ce_reg <= 1'b0; end else begin ce_reg <= clken_in; end end wire ram_wrclocken; assign ram_wrclocken = ce_reg;
VHDL RTL for Clock Enable
ENTITY mem_enable_vhd IS PORT( clock : in std_logic; freeze : in std_logic; clken_in : in std_logic; ram_wrclocken : out std_logic); END mem_enable_vhd; ARCHITECTURE behave OF mem_enable_vhd is SIGNAL ce_reg: std_logic; SIGNAL ce_delay: std_logic_vector(1 downto 0); BEGIN PROCESS (clock, freeze) BEGIN IF ((clock'EVENT AND clock = '1') or (freeze'EVENT AND freeze = '1')) THEN IF (freeze = '1') THEN ce_delay <= "00"; ELSE ce_delay <= ce_delay(0) & '1'; END IF; END IF; END PROCESS; PROCESS (clock, ce_delay(1)) BEGIN IF ((clock'EVENT AND clock = '1') or (ce_delay(1)'EVENT AND ce_delay(1) = '0')) THEN IF (ce_delay(1) = '0') THEN ce_reg <= '0'; ELSE ce_reg <= clken_in; END IF; END IF; END PROCESS; ram_wrclocken <= ce_reg; END ARCHITECTURE behave;
1.6.10.1. Clock Gating
Implement the gating circuitry in the static region, and feed it to the PR region in which the initialized memories are being implemented. Clock gating is logically equivalent to using clock enable on the memories. This method provides the following benefits:
- Uses the enable port of the global clock buffers to disable the clock before starting the partial reconfiguration operation. Also enables the clock on PR completion.
- Ensures that the clock does not switch during reconfiguration, and requires no additional logic to avoid spurious writes.
1.7. Hierarchical Partial Reconfiguration
Hierarchical partial reconfiguration (HPR) is an extension of partial reconfiguration (PR), where you contain one PR region within another PR region. You can create multiple personas for both the child and parent partitions. You nest the child partitions within their parent partitions. Reconfiguring a parent partition does not impact the operation in the static region, but replaces the child partitions of the parent region with default child partition personas.
- Create a base revision for the design and export the static region, as Step 7: Compile the Base Revision and Export the Static Region describes.
- Create the implementation revision for each persona, as Step 8: Setup PR Implementation Revisions describes, and export the parent partitions.
- Specify the .qdb file partition for the static and parent regions.
- Specify the corresponding entity for the parent or child.
1.7.1. Using Parent QDB Files from Different Compiles
Figure 31 shows an HPR design hierarchy with the following characteristics:
- The blue and orange regions represent the HPR parent regions.
- The yellow and green boxes represent the child PR regions.
- The blue HPR parent has two personas, blue_1 and blue_2.
- For the yellow child region, the default persona that is compiled with parent blue_1 is yellow_1_1.
- The second child persona that can be compiled by blue_1 is yellow_2_1.
- The orange HPR parent has the same characteristics as the blue HPR parent.
Considering these HPR design characteristics, the following describes one possible HPR compilation flow:
HPR Compilation Flow A:
- Blue_1, yellow_1_1, orange_1, green_1_1.
- Blue_1.qdb, yellow_1_2, orange_1.qdb, green_1_2
- Blue_2, yellow_2_1, orange_2, green_2_1
- Blue_2.qdb, yellow_2_2, orange_2.qdb, green_2_2
In Flow A, in steps 2 and 4, the parent region .qdb files come from the same implementation compile. Step 2 uses blue_1.qdb and orange_1.qdb that step 1 generates in the same implementation compile.
HPR also supports import of the parent and child PR partitions from different implementation compiles:
HPR Compilation Flow B:
- Blue_1, yellow_1_1, orange_1, green_1_1.
- Blue_2, yellow_2_1, orange_2, green_2_1
- Blue_1.qdb, yellow_1_2, orange_2.qdb, green_2_2
- Blue_2.qdb, yellow_2_2, orange_1.qdb, green_1_2
In Flow B, blue_1.qdb and orange_2.qdb come from two different implementation compiles. Step 1 generates blue_1.qdb. Step 2 implementation compile generates orange_2.qdb.
1.8. Partial Reconfiguration Design Timing Analysis
The interface between partial and static partitions remains the same for each PR implementation revision. Perform timing analysis on each PR implementation revision to ensure that there are no timing violations. To ensure timing closure of a design with multiple PR regions, you can create aggregate revisions for all possible PR region combinations for timing analysis.
1.8.1. Running Timing Analysis on Aggregate Revisions
- To open the Revisions dialog box, click Project > Revisions.
- To create a new revision, double-click <<new revision>>.
- Specify the Revision name and select the base revision for Based on Revision.
-
To export the post-fit database from the base compile (static
partition), type the following command in the
Intel®
Quartus® Prime
shell:
quartus_cdb <project name> <base revision> --export_block \ "root_partition" --snapshot final --file \ "<base revision name>.qdb"
Note: Ensure that you include all the .sdc and .ip files for the static and PR regions. To detect the clocks, ensure that the .sdc file for the PR Controller IP follows the entry of any .sdc file that creates the clocks that the IP core uses. You facilitate this order by ensuring the .ip file for the PR Controller IP comes after any .ip or .sdc files that you use to create these clocks in the .qsf file for the project revision. Refer to Partial Reconfiguration Solutions IP User Guide for more information. -
To export the post-fit database from multiple personas (for the PR
implementation revisions), type the following commands in the
Intel®
Quartus® Prime shell:
quartus_cdb <project name> -c <PR1 revision> --export_block \ <PR1 Partition name> --snapshot final --file "pr1.qdb" quartus_cdb <project name> -c <PR2 revision> --export_block \ <PR2 Partition name> --snapshot final --file "pr2.qdb"
-
To import the post-fit databases of the static region as an aggregate
revision, type the following commands in the
Intel®
Quartus® Prime
shell:
quartus_cdb <project name> -c <aggr_rev> --import_block \ "root_partition" --file "<base revision name>.qdb" quartus_cdb <project name> -c <aggr_rev> --import_block \ <PR1 partition name> --file "pr1.qdb" quartus_cdb <project name> -c <aggr_rev> --import_block \ <PR2 Partition name> --file "pr2.qdb"
-
To integrate post-fit database of all the partitions, type the following command in the
Intel®
Quartus® Prime shell:
quartus_fit <project name> -c <aggr_rev>
Note: The Fitter verifies the legality of the post-fit database, and combines the netlist for timing analysis. The Fitter does not reroute the design. -
To perform timing analysis on the aggregate revision, type the following command in the
Intel®
Quartus® Prime shell:
quartus_sta <proj name> -c <aggr_rev>
- Run timing analysis on aggregate revision for all possible PR persona combinations. If a specific persona fails timing closure, recompile the persona and perform timing analysis again.
1.9. Partial Reconfiguration Design Simulation
The Intel® Quartus® Prime Pro Edition software supports simulation of PR persona transitions through the use of simulation multiplexers. You use the simulation multiplexers to change which persona drives logic inside the PR region during simulation. This simulation allows you to observe the resulting change and the intermediate effect in a reconfigurable partition.
Similar to non-PR design simulations, preparing for a PR simulation involves setting up your simulator working environment, compiling simulation model libraries, and running your simulation. The Intel® Quartus® Prime software provides simulation components to help simulate a PR design, and can generate the gate-level PR simulation models for each persona. Use either the behavioral RTL or the gate-level PR simulation model for simulation of the PR personas. The gate-level PR simulation model allows for accurate simulation of registers in your design and reset sequence verification. These technology-mapped registers do not assume initial conditions.
You can use the PR mode of the EDA netlist writer to generate the gate level netlist of a PR region. Refer to the "EDA Netlist Writer and Gate Level-Netlists" section of the Intel® Quartus® Prime Pro Edition User Guide: Third Party Simulation.
1.9.1. Partial Reconfiguration Simulation Flow
- System-level preparation for a PR event.
- Retrieval of the partial bitstream from memory.
- Transmission of the partial bitstream to the PR control block or SDM.
- Resulting change in the design as a new persona becomes active.
- Post-PR system coordination.
- Use of the new persona in the system.
1.9.1.1. Simulating PR Persona Replacement
- altera_pr_wrapper_mux_in
- altera_pr_wrapper_mux_out
- altera_pr_persona_if (SystemVerilog interface allows you to connect the wrapper multiplexers to a testbench driver)
RTL Wrapper for PR Persona Switching Simulation
The pr_activate input of the altera_pr_wrapper_mux_out module enables the MUX to output X. This functionality allows the simulation of unknown outputs from the PR persona, and also verifies the normal operation of the design’s freeze logic. The following code corresponds to the simulation of PR persona switching, shown in the above figure:
module pr_core_wrapper ( input wire a, input wire b, output wire o ); localparam ENABLE_PERSONA_1 = 1; localparam ENABLE_PERSONA_2 = 1; localparam ENABLE_PERSONA_3 = 1; localparam NUM_PERSONA = 3; logic pr_activate; int persona_select; altera_pr_persona_if persona_bfm(); assign pr_activate = persona_bfm.pr_activate; assign persona_select = persona_bfm.persona_select; wire a_mux [NUM_PERSONA-1:0]; wire b_mux [NUM_PERSONA-1:0]; wire o_mux [NUM_PERSONA-1:0]; generate if (ENABLE_PERSONA_1) begin localparam persona_id = 0; `ifdef ALTERA_ENABLE_PR_MODEL assign u_persona_0.altera_sim_pr_activate = pr_activate; `endif pr_and u_persona_0 ( .a(a_mux[persona_id]), .b(b_mux[persona_id]), .o(o_mux[persona_id]) ); end endgenerate generate if (ENABLE_PERSONA_2) begin localparam persona_id = 1; `ifdef ALTERA_ENABLE_PR_MODEL assign u_persona_1.altera_sim_pr_activate = pr_activate; `endif pr_or u_persona_1 ( .a(a_mux[persona_id]), .b(b_mux[persona_id]), .o(o_mux[persona_id]) ); end endgenerate generate if (ENABLE_PERSONA_3) begin localparam persona_id = 2; `ifdef ALTERA ENABLE PR MODEL assign u_persona_2.altera_sim_pr_activate = pr_activate; `endif pr_empty u_persona_2 ( .a(a_mux[persona_id]), .b(b_mux[persona_id]), .o(o_mux[persona_id]) ); end endgenerate altera_pr_wrapper_mux_in #(.NUM_PERSONA(NUM_PERSONA), .WIDTH(1)) \ u_a_mux(.sel(persona_select), .mux_in(a), .mux_out(a_mux)); altera_pr_wrapper_mux_in #(.NUM_PERSONA(NUM_PERSONA), .WIDTH(1)) \ u_b_mux(.sel(persona_select), .mux_in(b), .mux_out(b_mux)); altera_pr_wrapper_mux_out #(.NUM_PERSONA(NUM_PERSONA), .WIDTH(1)) \ u_o_mux(.sel(persona_select), .mux_in(o_mux), .mux_out(o), .pr_activate \ (pr_activate)); endmodule
1.9.1.2. altera_pr_persona_if Module
interface altera_pr_persona_if; logic pr_activate; int persona_select; event report_storage_if_x_event; event report_storage_if_1_event; event report_storage_if_0_event; event report_storage_event; initial begin pr_activate <= 1'b0; end endinterface : altera_pr_persona_ifThe <QUARTUS_INSTALL_DIR> /eda/sim_lib/altera_lnsim.sv file defines the altera_pr_persona_if component.
1.9.1.3. altera_pr_wrapper_mux_out Module
module altera_pr_wrapper_mux_out #( parameter NUM_PERSONA = 1, parameter WIDTH = 1, parameter [0:0] DISABLED_OUTPUT_VAL = 1'bx ) ( input int sel, input wire [WIDTH-1 : 0] mux_in [NUM_PERSONA-1:0], output reg [WIDTH-1:0] mux_out, input wire pr_activate ); always_comb begin if ((sel < NUM_PERSONA) && (!pr_activate)) mux_out = mux_in[sel]; else mux_out = {WIDTH{DISABLED_OUTPUT_VAL}}; end endmodule : altera_pr_wrapper_mux_outThe <QUARTUS_INSTALL_DIR> /eda/sim_lib/altera_lnsim.sv file defines the altera_pr_wrapper_mux_out component.
1.9.1.4. altera_pr_wrapper_mux_in Module
module altera_pr_wrapper_mux_in#( parameter NUM_PERSONA = 1, parameter WIDTH = 1, parameter [0:0] DISABLED_OUTPUT_VAL = 1'bx ) ( input int sel, input wire [WIDTH-1:0] mux_in, output reg [WIDTH-1 : 0] mux_out [NUM_PERSONA-1:0] ); always_comb begin for (int i = 0; i < NUM_PERSONA; i++) if (i == sel) mux_out[i] = mux_in; else mux_out[i] = {WIDTH{DISABLED_OUTPUT_VAL}}; end endmodule : altera_pr_wrapper_mux_inThe <QUARTUS_INSTALL_DIR> /eda/sim_lib/altera_lnsim.sv file defines the altera_pr_wrapper_mux_in component.
1.10. Partial Reconfiguration Design Debugging
The following Intel® FPGA IP cores support system-level debugging in the static region of a PR design:
- In-System Memory Content Editor
- In-System Sources and Probes Editor
- Virtual JTAG
- Nios® II JTAG Debug Module
- Signal Tap Logic Analyzer
In addition, the Signal Tap logic analyzer allows you to debug the static or partial reconfiguration (PR) regions of the design. If you only want to debug the static region, you can use the In-System Sources and Probes Editor, In-System Memory Content Editor, or System Console with the JTAG Avalon Master Bridge.
1.10.1. Debugging PR Designs with the Signal Tap Logic Analyzer
Perform the following steps during the early planning stage, to ensure you can use Signal Tap to debug your static as well as PR region:
- Instantiate the SLD JTAG Bridge Agent IP in the static region.
- Instantiate the SLD JTAG Bridge Host IP in the PR region of the default persona.
- Instantiate the SLD JTAG Bridge Host IP for each of the personas when creating revisions for the personas.
The Signal Tap logic analyzer uses the hierarchical debug capabilities provided by the Intel® Quartus® Prime software to tap signals in the static and PR regions simultaneously.
You can debug multiple personas present in your PR region, as well as multiple PR regions. For complete information on the debug infrastructure using hierarchical hubs, refer to Intel Quartus Prime Pro Edition User Guide: Debug Tools.
1.11. PR Bitstream Security Verification ( Intel Stratix 10 Designs)
When you license and enable PR bitstream security verification, the Programmer performs bit ownership, signal peek, poke, and contention checks prior to PR bitstream generation. If the Programmer cannot verify the PR persona .pmsf file against the Secure Mask Settings file (.smsf), PR bitstream generation terminates.
PR bitstream security verification enables multi-tenant FPGA usage, such as when a Platform Owner partitions a single device to host multiple third-party Clients. The Platform Owner may not trust the Clients, and the Clients may not trust each other, but the Clients trust the Platform Owner. PR bitstream security verification provides the Platform Owner and Clients protection from any party corrupting the proprietary server, Client configurations, or from initiating a peek or poke attack by a subsequent partial reconfiguration.
In such multi-tenant scenarios, PR bitstream security verification can protect against the following known threats:
- Changing bits in a PR region owned by another party—a PR persona can potentially inject a change in functionality to another client’s persona and cause a DOS or PDOS attack, cause an unintended function, or redirect a signal from the unowned persona.
- Poke Attack—a PR persona can potentially corrupt other PR regions input data by poking on its wires.
- Peek Attack—a PR persona can potentially view values on routing wires from other PR regions to snoop on their data.
- Excessive Power Consumption—PR personas can potentially cause excessive FPGA power consumption due to wire contention inside the PR region.
1.11.1. PR Bitstream Security Use Case ( Intel Stratix 10 Designs)
A Cloud Service Provider partitions the FPGA into various PR regions to host multiple third-party clients. The Cloud Service Provider uses this partitioned design for the base device configuration. After the base configuration loads on the device, PR bitstream security allows only verified PR region persona to load into the corresponding PR region.
1.11.2. Using PR Bitstream Security Verification ( Intel Stratix 10 Designs)
The .pmsf contains comprehensive information that the Programmer requires to generate the PR bitstream for a Client region, including the actual bit settings, a region mask, and all the auxiliary bit masks. The .smsf contains a region ownership mask and comprehensive information to detect a peek or poke attack by the PR region’s persona.
Thereafter, the Programmer requires both the private .pmsf and public .smsf to generate the PR bitstream for this PR region, ensuring that the PR persona can only change bits that the persona owns. The Platform Owner may or may not release .smsf files to third-party Clients as part of the PR region collateral. The Platform Owner uses the .smsf to generate the PR bitstream from Client's .pmsf for this PR region with the Programmer.
- Obtain the license file to enable generation of .smsf files for PR regions during base compilation, and to perform PR bitstream security verification during PR bitstream generation in the Programmer. To obtain the license, login or register for a My-Intel account, and then submit an Intel® Premier Support case requesting the license key.
- To add the license file to the Intel® Quartus® Prime Pro Edition software, click Tools > License Setup and specify the feature License File.
-
To enable PR security validation features, add the following line to
the project .qsf:
set_global_assignment -name PR_SECURITY_VALIDATION on
- Compile the base revision.
- Following base compilation, view the Assembler reports to view the generated .smsf files required for bitstream generation for each PR region.
- The Platform Owner may release .smsf files to third-party clients as part of the PR region collateral. The Client provides the private .pmsf to the Platform Owner to verify PR security of the PR Persona configuration and generate validated PR bitstreams.
-
To validate PR security of the Client's .pmsf, the Platform Owner specifies the .smsf and corresponding .pmsf files at
the Programmer command line to generate the validated PR bitstreams:
quartus_cpf -c –-smsf=<smsf_file> <pmsf_file> <output_file>
1.12. PR Bitstream Compression and Encryption ( Intel Arria 10 and Intel Cyclone 10 GX Designs)
Compress the base and PR programming bitstreams independently, based on your design requirements. When encrypting only the base image, specify whether or not to encrypt the PR images. The following guidelines apply to PR bitstream compression and encryption:
-
You can encrypt the base and PR image independently. You can use a non-volatile encryption key for the base image, and a volatile encryption key for the PR image.
- Refer to Table 8 to ensure the correct Clock-to-Data (CD) ratio setting for encryption or compression.
Enable enhanced decompression by turning on the Enable enhanced decompression option when specifying the parameters in the IP Catalog or Platform Designer parameter editors.
1.12.1. Generating an Encrypted PR Bitstream ( Intel Arria 10 or Intel Cyclone 10 GX Designs)
- Create a 256-bit key file (.key).
-
To generate the key programming file (.ekp) from
the
Intel®
Quartus® Prime shell, type the following command:
quartus_cpf --key <keyfile>:<keyid> \ <base_sof_file> <output_ekp_file>
For example:
quartus_cpf --key my_key.key:key1 base.sof key.ekp
-
To generate the encrypted PR bitstream (.rbf), run
the following command:
quartus_cpf -c <pr_pmsf_file> <pr_rbf_file> qcrypt -e --keyfile=<keyfile> --keyname=<keyid> –lockto=\ <qlk file> --keystore=<battery|OTP> \ <pr_rbf_file> <pr_encrypted_rbf_file>
- lockto—specifies the encryption lock.
- keystore—specifies the volatile key (battery) or the non-volatile key (OTP).
For example:
quartus_cpf -c top_v1.pr_region.pmsf top_v1.pr_region.rbf \ qcrypt -e --keyfile=my_key.key --keyname=key1 --keystore=battery \ top_v1.pr_region.rbf top_v1_encrypted.rbf
-
To program the key file as volatile key (default) into the device, type the following
command:
quartus_pgm -m jtag -o P;<output_ekp_file>
For example:
quartus_pgm -m jtag -o P;key.ekp
-
To program the base image into the device, type the following command:
quartus_pgm -m jtag -o P;<base_sof_file>
For example:
quartus_pgm -m jtag -o P;base.sof
-
To partially reconfigure the device with the encrypted bitstream, type the following
command:
quartus_pgm -m jtag --pr <output_encrypted_rbf_file>
For example:
quartus_pgm -m jtag --pr top_v1_encrypted.rbf
qcrypt generates an error if the Enable bitstream compatibility check parameter is enabled for an instance of the Partial Reconfiguration Controller Intel® Arria® 10/Cyclone 10 FPGA IP. Use one of the following methods to avoid this error:
- Use the Convert Programming Files dialog box, rather than qcrypt, to generate the encrypted PR bitstream, as Generating PR Bitstream Files describes.
- If you want use qcrypt with Intel® Arria® 10 or Intel® Cyclone® 10 GX designs, regenerate the Partial Reconfiguration Controller IP without the Enable bitstream compatibility check option enabled, and with the Enable hierarchical PR support option enabled, as Adding the Partial Reconfiguration Controller Intel® Arria® 10/Cyclone 10 FPGA IP describes. Recompile the design before regenerating the PR bitstream.
1.12.2. Clock-to-Data Ratio for Bitstream Encryption and Compression ( Intel Arria 10 or Intel Cyclone 10 GX Designs)
Configuration Data Width | AES Encryption | Basic Compression | CD Ratio |
---|---|---|---|
x8 | Off | Off | 1 |
Off | On | 2 | |
On | Off | 1 | |
x16 | Off | Off | 1 |
Off | On | 4 | |
On | Off | 2 | |
x32 | Off | Off | 1 |
Off | On | 8 | |
On | Off | 4 |
Use the exact CD ratio that the Valid combinations and CD Ratio for Bitstream Encryption and Compression table specifies for different bitstream types. The CD ratio for plain .rbf must be 1. The CD ratio for compressed .rbf must be 2, 4 or 8, depending on the width. Do not specify the CD ratio as the necessary minimum to support different bitstream types.
1.12.3. Data Compression Comparison
Standard compression results in a 30-45% decrease in .rbf size. Use of the enhanced data compression algorithm results in 55-75% decrease in .rbf size. The algorithm increases the compression at the expense of additional core area required to implement the compression algorithm.
The following figure shows the compression ratio comparison across PR designs with varying degrees of Logic Element (LE):
1.13. Avoiding PR Programming Errors
PR Programming Guideline | Description |
---|---|
Device in project must match device on board | Confirm the target FPGA device that you specify for the project matches the device on the development kit you target. These two devices must be the same. Click Assignments > Device to view the target device. |
Programmer versions must match | When using the Intel® Quartus® Prime Programmer for PR programming, confirm that the Programmer version matches the Intel® Quartus® Prime version that you use for compilation. A mismatch between the Programmer and Intel® Quartus® Prime software version can occur if you compile on one machine, and then program on a different machine with a different Intel® Quartus® Prime version. The software version match is especially critical for Intel® Stratix® 10 and Intel® Agilex™ designs because the PR configuration hardware has dependencies inside the Programmer. |
Specify a lower JTAG clock frequency | Lower the JTAG clock frequency to 6MHz:
|
Close timing for all revisions | Confirm that each project revision closes timing
after design compilation:
|
1.14. Exporting a Version-Compatible Compilation Database for PR Designs
This technique is helpful when you want to compile and generate bitstreams for the PR implementation revisions with a later version of the Intel® Quartus® Prime software. Configuration bitstreams are not version compatible, and you must generate all bitstreams from the same version of Intel® Quartus® Prime software.
After migrating the base revision to a later version of the Intel® Quartus® Prime software, the bitstream you generate is only compatible with bitstreams from PR implementation compilations using that same Intel® Quartus® Prime software version. Such a bitstream is incompatible with the PR bitstreams from an earlier version of the Intel® Quartus® Prime software.
Intel® Quartus® Prime Pro Edition Software Export Versions | Intel® Quartus® Prime Pro Edition Software Import Version | Intel® Stratix® 10 and Intel® Agilex™ Devices | Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices |
---|---|---|---|
18.0 | 19.1 | No Support. | Supports all devices. |
18.1 | 19.1 |
|
Supports all devices. |
19.1 | 19.3 |
|
Supports all devices. |
19.3 | 20.1 |
|
Supports all devices. |
20.1 | 20.3 |
|
Supports all devices. |
The following topics describe the version-compatible database generation flow and steps.
- Version-Compatible Database Flow for PR Designs
- Generating a Version-Compatible Compilation Database for PR Designs
Follow these steps to generate a version-compatible compilation database for PR designs:
1.14.1. Version-Compatible Database Flow for PR Designs
Migrating a design with a single PR region involves the following high-level steps:
- Perform initial compilation of the base revision in the Intel® Quartus® Prime software version N.
- Export a version-compatible database for the entire design in the Intel® Quartus® Prime software version N.
- Import the version-compatible database into the Intel® Quartus® Prime software version N+M.
- Generate the base revision .sof file and bitstreams with the Intel® Quartus® Prime Assembler version N+M.
- Export the static region .qdb in the Intel® Quartus® Prime software version N+M.
- Perform a PR implementation compile in the Intel® Quartus® Prime software version N+M.
1.14.2. Generating a Version-Compatible Compilation Database for PR Designs
- Export the entire compiled design from the
Intel®
Quartus® Prime software version N by clicking Project > Export Design, or by command
line:
quartus_cdb <project> -c <base_revision> --export_design --snapshot final \ --file <base_revision>.qdb
- Import the compiled design to the
Intel®
Quartus® Prime software version N+M by clicking Project > Import Design, or by command
line:
quartus_cdb <project> -c <base_revision_import> --import_design --file \ <base_revision>.qdb
Note: Whenever possible, import the design into a different working directory than the directory that you use to compile the base design. If you must use the same directory for import and for compiling the base design, make a backup copy of your compiled design by archiving that design with qdb/* included, or make a copy of the entire directory and subdirectories elsewhere. You must also remove the old database directory qdb/* and all the bitstream related files (*.sof, *.msf, *.pmsf). - Rerun the finalize stage of the Fitter in the
Intel®
Quartus® Prime Pro Edition software version N+M by clicking Processing > Start > Start Fitter (Finalize), or by command
line:
quartus_fit <project> -c <base_revision_import> --finalize
- Run the Assembler in the
Intel®
Quartus® Prime Pro Edition software version N+M to regenerate the static region bitstream by
clicking Processing > Start > Start Assembler, or by command
line:
quartus_asm <project> -c <base_revision_import>
- Export the static region .qdb in the
Intel®
Quartus® Prime Pro Edition software version N+M by clicking Project > Export Design Partition, or by command
line:
quartus_cdb <project> -c <base_revision_import> --export_block \ root_partition --snapshot final --file --include_sdc_entity_in_partition static.qdb
Note: When exporting the base revision and the static partition, you must include any .sdc files that apply to the partition, by using the include_sdc_entity_in_partition option. - Compile each implementation revision in
Intel®
Quartus® Prime Pro Edition software version N+M, using the static revision .qdb that you exported in the previous
step.
quartus_sh –flow compile <project> –c <impl_rev>
1.15. Creating a Partial Reconfiguration Design Revision History
Document Version | Intel® Quartus® Prime Version | Changes |
---|---|---|
2020.12.11 | 20.3 |
|
2020.09.28 | 20.3 |
|
2020.08.07 | 20.2 |
|
2020.06.22 | 20.2 |
|
2020.05.11 | 20.1 |
|
2020.04.13 | 20.1 |
|
2019.11.18 | 19.3.0 |
|
2019.09.30 | 19.3.0 |
|
2019.06.10 | 19.1.0 |
|
2019.04.22 | 19.1.0 |
|
2019.04.01 | 19.1.0 |
|
2018.12.30 | 18.1.1 |
|
2018.10.24 | 18.1.0 |
|
2018.09.24 | 18.1.0 |
|
2018.07.18 | 18.0.0 |
|
2018.06.18 | 18.0.0 |
|
2018.05.29 | 18.0.0 |
|
2018.05.07 | 18.0.0 |
|
2017.11.06 | 17.1.0 |
|
2017.05.08 | 17.0.0 |
|
10.31.2016 | 16.1.0 |
|
2. Partial Reconfiguration Solutions IP User Guide
Instantiate one or more of these IP cores to implement handshake and freeze logic for PR functionality in your design. Alternatively, create your own PR handshake and freeze logic that interfaces with the PR region.
Intel® FPGA IP | Description | Usage |
---|---|---|
Partial Reconfiguration Controller Intel® FPGA IP |
Dedicated IP component that sends the partial reconfiguration bitstream for the Intel® Stratix® 10 or Intel® Agilex™ FPGAs. The PR bitstream performs reconfiguration by adjusting CRAM bits in the FPGA. |
One instance per Intel® Stratix® 10 or Intel® Agilex™ FPGA |
Partial Reconfiguration External Configuration Controller Intel® FPGA IP | IP component that supports Intel® Stratix® 10 and Intel® Agilex™ FPGA partial reconfiguration via an external source over dedicated PR pins.4 | One instance per Intel® Stratix® 10 or Intel® Agilex™ FPGA for external configuration |
Partial Reconfiguration Controller Intel® Arria® 10/Cyclone 10 FPGA IP |
Dedicated IP component that sends the partial reconfiguration bitstream to the Intel® Arria® 10 or Intel® Cyclone® 10 GX FPGA. The PR bitstream performs reconfiguration by adjusting CRAM bits in the FPGA. |
One instance per Intel® Arria® 10 or Intel® Cyclone® 10 GX FPGA, internal or external configuration. |
Partial Reconfiguration Region Controller Intel® FPGA IP |
Provides a standard Avalon® memory-mapped interface to the block that controls handshaking with the PR region. Ensures that PR region stops, resets, and restarts, according to the PR handshake. |
One instance per PR region. |
Avalon® Memory-Mapped Partial Reconfiguration Freeze Bridge Intel® FPGA IP |
Provides freeze capabilities to the PR region for Avalon® memory-mapped interfaces. |
One instance for each interface in each PR region. |
Avalon® Streaming Partial Reconfiguration Freeze Bridge Intel® FPGA IP |
Provides freeze capabilities to the PR region for Avalon® streaming interfaces. |
One instance for each interface in each PR region. |
2.1. Internal and External PR Host Configurations
2.2. Partial Reconfiguration Controller Intel FPGA IP
2.2.1. Memory Map
Name | Address Offset | Width | Access | Description |
---|---|---|---|---|
PR_DATA | 0x00 | 32 | Write |
Every data write to this address indicates this bitstream is sending to the IP core. Width is set by the Input data width parameter. |
PR_CSR | 0x01 | 32 | Read or Write | Control and status registers with the following
offset bits:
|
PR_SW_VER | 0x02 | 32 | Read | Read-only SW version register. Register is currently 0xBA500000. |
2.2.2. Parameters
The Partial Reconfiguration Controller Intel® FPGA IP supports customization of the following parameters.
Parameter |
Value |
Description |
---|---|---|
Enable Avalon-ST sink or Avalon-MM slave interface | Avalon-ST/Avalon-MM |
Enables the controller's Avalon streaming sink or Avalon memory-mapped slave interface. |
Input data width | <bits> |
Specifies the size of the controller's data conduit interface in bits. The IP supports device widths of 32 and 64. |
Enable interrupt interface |
Yes/No |
Enables interrupt assertion for detection of incompatible bitstream, CRC_ERROR, PR_ERROR, or successful partial reconfiguration. Upon interrupt, query PR_CSR[4:2] for status. Write a 1 to PR_CSR[5] to clear the interrupt. Use only together with the Avalon® memory-mapped slave interface. |
Enable protocol error | Reads out the error bit from the CSR register. |
2.2.3. Ports
Port Name | Width | Direction | Function |
---|---|---|---|
reset |
1 |
Input |
Asynchronous reset for the PR Controller IP core. Resetting the PR Controller IP core during a partial reconfiguration operation can cause the device to lock up. |
clk |
1 |
Input |
Input clock to the PR Controller IP core. The input clock must be free-running. The IP core has a maximum clock frequency of 200 MHz. |
Port Name | Width | Direction | Function |
---|---|---|---|
pr_start |
1 |
Input |
A signal arriving at this port asserted high initiates a PR event. You must assert this signal high for a minimum of one clock cycle, and de-assert it low, prior to the end of the PR operation. |
avst_sink_data[] |
32|64 |
Input |
Avalon® streaming data signal that is synchronous with the rising edge of the clk signal. The Input data width parameter specifies this port width. |
avst_sink_valid |
1 |
Input |
Avalon® streaming data valid signal that indicates the avst_sink_data port contains valid data. |
avst_sink_ready |
1 |
Output |
Avalon® streaming ready signal that indicates the device is ready to read the streaming data on the avst_sink_data port whenever the avst_sink_valid signal asserts high. Stop sending valid data when this port is low. |
status[2..0] |
3 |
Output |
A 3-bit error output that indicates the status of a PR event. Once the outputs latch high as follow, you can only reset the outputs at the beginning of the next PR event: 3’b000 – power-up nreset asserted 3’b001 – configuration system is busy 3’b010 – PR operation is in progress 3’b011 – PR operation successful 3’b100 – PR_ERROR is triggered 3’b101 – Reserved 3'b110 – Reserved 3'b111 – Reserved |
protocol_error | 1 | Output | Reads out the error bit from the CSR register. |
Port Name | Width | Direction | Function |
---|---|---|---|
avmm_slave_address |
4 |
Input |
Avalon® memory-mapped address bus in the unit of Word addressing. |
avmm_slave_read |
1 |
Input |
Avalon® memory-mapped read control. |
avmm_slave_readdata |
32 |
Output |
Avalon® memory-mapped read data bus. |
avmm_slave_write |
1 |
Input |
Avalon® memory-mapped write control. |
avmm_slave_writedata |
32 |
Input |
Avalon® memory-mapped write data bus. |
avmm_slave_waitrequest |
1 |
Output |
Upon assertion, indicates that the IP is busy and the IP is unable to respond to a read or write request. |
irq |
1 |
Output |
Interrupt signal when you enable the Enable interrupt interface parameter. |
2.2.4. Timing Specifications
2.3. Partial Reconfiguration Controller Intel Arria 10 /Cyclone 10 FPGA IP
2.3.1. Slave Interface
The Partial Reconfiguration Controller Intel® Arria® 10 /Cyclone 10 FPGA IP provides an Avalon® memory-mapped slave interface to read and write to PR configuration registers.
Name | Address Offset | Access | Description |
---|---|---|---|
PR_DATA | 0x00 | Write |
Every data write to this address indicates this bitstream is sent to the IP core. Performing a read on this address returns all 0's. |
PR_CSR | 0x01 | Read or Write | Control and status registers. |
Version Register | 0x02 | Read-Only |
Read-only SW version register. Register is currently 0xAA500003 |
PR Bitstream ID | 0x03 | Read-Only | Read-only PR POF ID register |
Bit Offset | Description |
---|---|
0 |
Read and write control register for pr_start signal. Refer to Ports for details on the pr_start signal. pr_start = PR_CSR[0] The IP core deasserts PR_CSR[0] to value 0 automatically, one clock cycle after the PR_CSR[0] asserts. This streamlines the flow to avoid manual assertion and de-assertion of this register to control pr_start signal. |
1 | Reserved. |
2-4 |
Read-only status register for status[2:0] signal. PR_CSR[4:2] = status[2:0] Refer to Ports for details on the status signals. |
5 |
Read and clear bit for interrupt. If you enable the interrupt interface, reading this bit returns the value of the irq signal. Writing a 1 clears the interrupt. If you disable the interrupt interface, reading this bit always returns a value of 0. |
0-31 | Reserved bits. Depends on the Avalon® memory-mapped data bus width. |
2.3.2. Reconfiguration Sequence
- Avalon® memory-mapped master component writes 0x01 to IP address offset 0x1 to trigger PR operation.
- Optionally poll the status register until PR Operation in Progress. Not polling results in waitrequest on first word.
- Avalon® memory-mapped master component writes PR bitstream to IP address offset 0x0, until all the PR bitstream writes. When enhanced decompression is on, waitrequest activates throughout the PR operation. Ensure that your master can handle waitrequest from the slave interface.
- Avalon® memory-mapped master component reads the data from IP address offset 0x1 to check the status[2:0] value. Optionally, the Avalon® memory-mapped master component reads the status[2:0] of this IP during a PR operation to detect any early failure, for example, PR_ERROR.
2.3.3. Interrupt Interface
The IP core asserts irq during the following events:
Status Code | Event |
---|---|
3'b001 | PR_ERROR occurred. |
3'b010 | CRC_ERROR occurred. |
3'b011 | The IP core detects an incompatible bitstream. |
3'b101 | The result of a successful PR operation. |
After irq asserts, the master performs one or more of the following:
- Query for the status of the PR IP core; PR_CSR[4:2].
- Carry out some action, such as error reporting.
- Once the interrupt is serviced, clear the interrupt by writing a "1" to PR_CSR[5].
2.3.4. Parameters
The Partial Reconfiguration Controller Intel® Arria® 10 /Cyclone 10 FPGA IP supports customization of the following parameters.
Parameter |
Value |
Description |
---|---|---|
Use as partial reconfiguration internal host | On|Off |
Enables the controller for use as an internal host. Enabling this option auto-instantiates prblock and crcblock WYSIWYG as part of your design. Disable this option to use the controller as an external host. Connect additional interface signals to the dedicated partial reconfiguration pins. |
Enable JTAG debug mode | On|Off |
Enables access to the controller by the Intel® Quartus® Prime Programmer for partial reconfiguration over a JTAG interface. |
Enable Avalon® -MM slave interface | On|Off | Enables the controller's Avalon® memory-mapped slave interface. When this setting is Off, the IP controller enables the conduit interface. |
Enable interrupt interface | On|Off | Enables interrupt assertion for detection of incompatible bitstream, CRC_ERROR, PR_ERROR, or successful partial reconfiguration. Upon interrupt, query PR_CSR[4:2] for status. Write a 1 to PR_CSR[5] to clear the interrupt. Use only together with the Avalon® memory-mapped slave interface. |
Enable freeze interface | On|Off |
Enables the controller's single-bit freeze interface. This interface identifies whether any region in the design is active or frozen for partial reconfiguration operations. Leave this interface off, and use the freeze interface from the Partial Reconfiguration Region Controller IP. |
Enable bitstream compatibility check | On|Off |
Enables bitstream compatibility checks during partial reconfiguration operation from the external host. Bitstream compatibility check automatically enables when you use partial reconfiguration by internal host. Specify the partial reconfiguration bitstream ID value if you enable this option for partial reconfiguration by external host. |
PR bitstream ID | <32-bit integer> |
Specifies a signed, 32-bit integer value of the partial reconfiguration bitstream ID for the external host. This value must match the partial reconfiguration bitstream ID that the Compiler generates for the target partial reconfiguration design. Locate the partial reconfiguration bitstream ID of the target partial reconfiguration design in the Assembler report (.asm.rpt). |
Input data width | 1|8|16|32 |
Specifies the size of the controller's data conduit interface in bits. Refer to Error Detection CRC Requirements. |
Clock-to-data ratio | 1|4|8 |
Specifies the clock-to-data ratio that corresponds with the partial reconfiguration bitstream data type. Refer to the Valid combinations and CD Ratio for Bitstream Encryption and Compression Table. |
Divide error detection frequency by | 1..256 |
Specifies the divide value of the internal clock. This value determines the frequency of the error detection CRC. The divide value must be a power of two. Refer to device documentation to determine the frequency of the internal clock for the device you select. Refer to Error Detection CRC Requirements. |
Enable enhanced decompression | On|Off |
Enable enhanced decompression of partial reconfiguration bitstreams. Note: You cannot use enhanced decompression together
with encryption simultaneously. Enhanced decompression is only
available with the Partial Reconfiguration Controller
Intel®
Arria® 10
/Cyclone 10 FPGA IP.
|
Parameter |
Value |
Description |
---|---|---|
Auto-instantiate partial reconfiguration control block | On|Off |
Automatically includes the partial reconfiguration control block in the controller. When using the controller as an internal host, disable this option to share the partial reconfiguration block with other IP cores. Rather, manually instantiate the partial reconfiguration control block, and connect the relevant signals to the controller. |
Auto-instantiate CRC block | On|Off | Automatically includes the CRC block within the controller. Leave this option enabled unless you plan to use single event upset (SEU) IP in the same PR design. If you disable this option, IP generation exports the crc_error_pin for manual connection to an external CRC block that you manually instantiate. If you disable this option and then subsequently leave the exported crc_error_pin floating, the PR operation is undetermined due to unexpected crc_error_pin. |
Generate timing constraints file | On|Off |
Automatically generates an appropriate Synopsys Design Constraints (.sdc) file to constrain the timing of the controller. Disable this option when providing timing constraints in another file. |
2.3.4.1. Error Detection CRC Requirements
PR IP Input Data Width | Configuration Mode | Enable Error Detection Check | PR Support |
---|---|---|---|
1, 8, 16 | Passive Parallel x1, x8, x16 | Off | Yes |
1, 8, 16 | Passive Parallel x1, x8, x16 | On | Yes, for all Divide error detection frequency by values |
32 | Passive Parallel x1, x8, x16 | Off | No support |
32 | Passive Parallel x1, x8, x16 | On | Yes, for only Divide error detection frequency by value 2 or 4 |
1, 8, 16, 32 | Passive Parallel x32 | Off | Yes |
1, 8, 16, 32 | Passive Parallel x32 | On | Yes, for all Divide error detection frequency by values |
2.3.5. Ports
Port Name | Width | Direction | Function |
---|---|---|---|
nreset |
1 |
Input |
Asynchronous reset for the PR Controller IP core. Resetting the PR Controller IP core during a partial reconfiguration operation initiates the withdrawal sequence. |
clk |
1 |
Input |
User input clock to the PR Controller IP core. The IP core has a maximum clock frequency of 100MHz. The IP core ignores this signal during JTAG debug operations. |
Port Name | Width | Direction | Function |
---|---|---|---|
freeze |
1 |
Output |
Active high signal that freezes the PR interface signals of any region undergoing partial reconfiguration. De-assertion of this signal indicates the end of PR operation. Use the Partial Reconfiguration Region Controller IP rather than the Partial Reconfiguration Controller IP freeze signal. |
Port Name | Width | Direction | Function |
---|---|---|---|
pr_start |
1 |
Input |
A 0 to 1 transition on this port initiates a PR event. You must assert this signal high for a minimum of one clock cycle, and de-assert the signal low prior to the end of the PR operation. This operation ensures the PR Controller IP core is ready to accept the next pr_start trigger event when the freeze signal is low. The PR Controller IP core ignores this signal during JTAG debug operations. |
data[] |
1, 8, 16, or 32 |
Input |
Selectable input PR data bus width, either x1, x8, x16, or x32. Once a PR event triggers, the PR event is synchronous with the rising edge of the clk signal, whenever the data_valid signal is high, and the data_ready signal is high. The PR Controller IP core ignores this signal during JTAG debug operations. |
data_valid |
1 |
Input |
A 0 to 1 transition on this port indicates the data[] port contains valid data. The PR Controller IP core ignores this signal during JTAG debug operations. |
data_ready |
1 |
Output |
A 0 to 1 transition on this port indicates the PR Controller IP core is ready to read the valid data on the data[] port, whenever the data_valid signal asserts high. The data sender must stop sending valid data if this port is low. This signal deasserts low during JTAG debug operations. |
status[2..0] |
1 |
Output |
A 3-bit output that indicates the status of PR events. When the IP detects an error (PR_ERROR, CRC_ERROR, or incompatible bitstream error), this signal latches high. This signal only resets at the beginning of the next PR event, when pr_start is high, and freeze is low. For example: 3’b000 – power-up or nreset asserts 3’b001 – PR_ERROR triggers 3’b010 – CRC_ERROR triggers 3’b011 – Incompatible bitstream error detection 3’b100 – PR operation in progress 3’b101 – PR operation passes 3'b110 – Reserved bit 3'b111 – Reserved bit |
Port Name | Width | Direction | Function |
---|---|---|---|
avmm_slave_address |
4 |
Input |
Avalon® memory-mapped address bus. The address bus is in the unit of Word addressing. The PR Controller IP core ignores this signal during JTAG debug operations. |
avmm_slave_read | 1 |
Input |
Avalon® memory-mapped read control. The PR Controller IP core ignores this signal during JTAG debug operations. |
avmm_slave_readdata | 32 |
Output |
Avalon® memory-mapped read data bus. The PR Controller IP core ignores this signal during JTAG debug operations. |
avmm_slave_write | 1 |
Input |
Avalon® memory-mapped write control. The PR Controller IP core ignores this signal during JTAG debug operations. |
avmm_slave_writedata | 32 |
Input |
Avalon® memory-mapped write data bus. The PR Controller IP core ignores this signal during JTAG debug operations. |
avmm_slave_waitrequest | 1 |
Output |
Indicates that the IP is busy. Also indicates that the IP core is unable to respond to a read or write request. The IP core pulls this signal high during JTAG debug operations. |
Port Name | Width | Direction | Function |
---|---|---|---|
irq |
1 |
Output |
The interrupt signal. |
Port Name | Width | Direction | Function |
---|---|---|---|
crc_error_pin |
1 |
Input |
Available when you use the PR Controller IP core as an External Host. Connect this port to the dedicated CRC_ERROR pin of the FPGA undergoing partial reconfiguration. |
Port Name | Width | Direction | Function |
---|---|---|---|
pr_ready_pin |
1 |
Input |
Connect this port to the dedicated PR_READY pin of the FPGA undergoing partial reconfiguration. |
pr_error_pin |
1 |
Input |
Connect this port to the dedicated PR_ERROR pin of the FPGA undergoing partial reconfiguration. |
pr_done_pin |
1 |
Input |
Connect this port to the dedicated PR_DONE pin of the FPGA undergoing partial reconfiguration. |
pr_request_pin |
1 |
Output |
Connect this port to the dedicated PR_REQUEST pin of the FPGA undergoing partial reconfiguration. |
pr_clk_pin |
1 |
Output |
Connect this port to the dedicated DCLK of the FPGA undergoing partial reconfiguration. |
pr_data_pin[31..0] |
16|32 |
Output |
Connect this port to the dedicated DATA[31..0] pins of the FPGA undergoing partial reconfiguration. |
2.3.6. Timing Specifications
The following notes correspond to locations (1) through (7) in the timing diagram:
- Assert pr_start signal high for a minimum of one clock cycle to initiate PR. Deassert pr_start before sending the last data.
- status[] signal updates after pr_start is acknowledged. This signal changes during a PR operation if CRC_ERROR, PR_ERROR, or bitstream incompatibility error occurs.
- status[] signal changes after a PR operation if CRC_ERROR asserts and no error occurs during the previous PR operation.
- There is no requirement to assert the data_valid signal at the same time as the pr_start signal. Provide the data[], and assert data_valid, when appropriate.
- Either drive the data_valid signal low after sending the last data, or continue to assert data_valid high with dummy data on data[] until the IP reads the end of PR from status[].
- data[] transfers only when data_valid and data_ready assert on the same cycle. Do not drive new data on the data bus, when both data_valid and data_ready are not high.
- The data_ready signal drives low after the PR IP Controller core receives the last data, or when the PR IP Controller cannot accept data.
2.3.7. PR Control Block and CRC Block Verilog HDL Manual Instantiation
The Partial Reconfiguration Controller Intel® Arria® 10 /Cyclone 10 IP includes the PR control block. However, if you create your own custom logic to perform the function of the IP core, you can manually instantiate the control block to communicate with the FPGA system.
The following example instantiates a PR control block inside a top-level Intel® Arria® 10 PR project, Chip_Top, in Verilog HDL:
Chip_Top: module Chip_Top ( //User I/O signals (excluding PR related signals) .. .. //PR interface and configuration signals declaration wire pr_request; wire pr_ready; wire pr_done; wire crc_error; wire dclk; wire [31:0] pr_data; twentynm_prblock m_pr ( .clk (dclk), .corectl (1'b1), .prrequest(pr_request), .data (pr_data), .error (pr_error), .ready (pr_ready), .done (pr_done) ); twentynm_crcblock m_crc ( .clk (clk), .shiftnld (1'b1), .crcerror (crc_error) ); endmodule
For more information about port connectivity for reading the Error Message Register (EMR), refer to the AN539: Test Methodology of Error Detection and Recovery using CRC.
2.3.8. PR Control Block and CRC Block VHDL Manual Instantiation
The following example shows manual instantiation of a PR control block inside your top-level Intel® Arria® 10 project, Chip_Top, in VHDL:
module Chip_Top is port ( --User I/O signals (excluding signals that relate to PR) .. .. ) -- Following shows the connectivity within the Chip_Top module Core_Top : Core_Top port_map ( .. .. ); m_pr : twentynm_prblock port map( clk => dclk, corectl =>'1', --1 - when using PR from inside --0 - for PR from pins; You must also enable -- the appropriate option in Quartus Prime settings prrequest => pr_request, data => pr_data, error => pr_error, ready => pr_ready, done => pr_done ); m_crc : twentynm_crcblock port map( shiftnld => '1', --If you want to read the EMR register when clk => dummy_clk, --error occurrs, refer to AN539 for the --connectivity for this signal. If you only want --to detect CRC errors, but plan to take no --further action, you can tie the shiftnld --signal to logical high. crcerror => crc_error );
2.3.8.1. PR Control Block and CRC Block VHDL Component Declaration
- Use the code sample below, containing the component
declaration in VHDL. This code performs the PR function from within the core
(code block within Core_Top).
module Chip_Top is port ( --User I/O signals (excluding signals that relate to PR) .. .. ) -- Following shows the connectivity within the Chip_Top module Core_Top : Core_Top port_map ( .. .. ); m_pr : twentynm_prblock port map( clk => dclk, corectl =>'1', --1 - when using PR from inside --0 - for PR from pins; You must also enable -- the appropriate option in Quartus Prime settings prrequest => pr_request, data => pr_data, error => pr_error, ready => pr_ready, done => pr_done ); m_crc : twentynm_crcblock port map( shiftnld => '1', --If you want to read the EMR register when clk => dummy_clk, --error occurrs, refer to AN539 for the --connectivity forthis signal. If you only want --to detect CRC errors, but plan to take no --further action, you can tie the shiftnld --signal to logical high. crcerror => crc_error );
Note: This VHDL example is adaptable for Verilog HDL instantiation. - Add additional ports to Core_Top to connect to both components.
- Follow these rules when connecting the PR control block to
the rest of your design:
- Set the corectl signal to ‘1’ (when using partial reconfiguration from core) or to ‘0’ (when using partial reconfiguration from pins).
- The corectl signal must match the Enable PR pins option setting in the Device and Pin Options dialog box (Assignments > Device > Device and Pin Options).
- When performing partial reconfiguration from pins, the Fitter automatically assigns the PR unassigned pins. Assign all the dedicated PR pins using Pin Planner ( Assignments > Pin Planner) or Assignment Editor (Assignments > Assignment Editor).
- When performing partial reconfiguration from the core logic, connect the prblock signals to either core logic or I/O pins, excluding the dedicated programming pin, such as DCLK.
2.3.9. PR Control Block Signals
Signal | Width | Direction | Description |
---|---|---|---|
pr_data | [31:0] | Input |
Carries the configuration bitstream.
|
pr_done | 1 | Output | Indicates that the PR process is complete. |
pr_ready | 1 | Output | Indicates that the control block is ready to accept PR data from the control logic. |
pr_error | 1 | Output | Indicates a partial reconfiguration error. |
pr_request | 1 | Input | Indicates that the PR process is ready to begin. |
corectl | 1 | Input |
Determines whether you are performing the partial reconfiguration internally, or through pins.
|
- You can specify a configuration width of 8, 16, or 32 bits, but the interface always uses 32 pins.
- All the inputs and outputs are asynchronous to the PR clock (clk), except data signal. data signal is synchronous to clk signal.
- PR clock must be free-running.
- data signal must be 0 while waiting for ready signal.
2.3.9.1. PR Control Block Signal Timing Diagrams
Successful PR Session ( Intel® Arria® 10 Example)
The following flow describes a successful Intel® Arria® 10 PR session:
- Assert PR_REQUEST and wait for PR_READY; drive PR_DATA to 0.
- The PR control block asserts PR_READY, asynchronous to clk.
- Start sending Raw Binary File (.rbf) to the PR control block, with 1 valid word per clock cycle. On .rbf file transfer completion, drive PR_DATA to 0. The PR control block asynchronously asserts PR_DONE when the control block completes the reconfiguration operation. The PR control block deasserts PR_READY on configuration completion.
- Deassert PR_REQUEST. The PR control block acknowledges the end of PR_REQUEST, and deasserts PR_DONE. The host can now initiate another PR session.
Unsuccessful PR Session with Configuration Frame Readback Error ( Intel Arria 10 Example)
- The PR control block internally detects a CRC error.
- The CRC control block then asserts CRC_ERROR.
- The PR control block asserts the PR_ERROR.
- The PR control block deasserts PR_READY, so that the host can withdraw the PR_REQUEST.
- The PR control block deasserts CRC_ERROR and clears the internal CRC_ERROR signal to get ready for a new PR session. The host can now initiate another PR session.
Unsuccessful PR Session with PR_ERROR ( Intel Arria 10 Example)
The following flow describes an Intel® Arria® 10 PR session with transmission error or configuration CRC error:
- The PR control block asserts PR_ERROR.
- The PR control block deasserts PR_READY, so that the host can withdraw PR_REQUEST.
- The PR control block deasserts PR_ERROR to get ready for a new PR session. The host can now initiate another PR session.
Late Withdrawal PR Session ( Intel Arria 10 Example)
The following flow describes a late withdrawal Intel® Arria® 10 PR session:
- The PR host can withdraw the request after the PR control block asserts PR_READY.
- The PR control block deasserts PR_READY. The host can now initiate another PR session.
2.3.10. Configuring an External Host for Intel Arria 10 or Intel Cyclone 10 GX Designs
To use an external host for your design:
- Click Assignments > Device > Device & Pin Options.
- Select the Enable PR Pins
option in the Device & Pin Options
dialog box. This option automatically creates the special partial
reconfiguration pins, and defines the pins in the device pin-out. This option
also automatically connects the pins to PR control block internal path. Note: If you do not select this option, you must use an internal or HPS host. You do not need to define pins in your design top-level entity.
- Connect these top-level pins to the specific ports in the PR control block.
The following table lists the PR pins that automatically constrain when you turn on Enable PR Pins, and the specific PR control block port connection to the pin:
Pin Name | Type | PR Control Block Port Name | Description |
---|---|---|---|
PR_REQUEST | Input | prrequest | Logic high on this pin indicates that the PR host is requesting partial reconfiguration. |
PR_READY | Output | ready | Logic high on this pin indicates that the PR control block is ready to begin partial reconfiguration. |
PR_DONE | Output | done | Logic high on this pin indicates that the partial reconfiguration is complete. |
PR_ERROR | Output | error | Logic high on this pin indicates an error in the device during partial reconfiguration. |
DATA[31:0] | Input | data | These pins provide connectivity for PR_DATA to transfer the PR bitstream to the PR controller. |
DCLK | Input | clk | Receives synchronous PR_DATA. |
- PR_DATA can be 8, 16, or 32-bits in width.
- Ensure that you connect the corectl port of the PR control block to 0.
Verilog RTL for External Host PR
module top( // PR control block signals input logic pr_clk, input logic pr_request, input logic [31:0] pr_data, output logic pr_error, output logic pr_ready, output logic pr_done, // User signals input logic i1_main, input logic i2_main, output logic o1 ); // Instantiate the PR control block twentynm_prblock m_prblock ( .clk(pr_clk), .corectl(1'b0), .prrequest(pr_request), .data(pr_data), .error(pr_error), .ready(pr_ready), .done(pr_done) ); // PR Interface partition pr_v1 pr_inst( .i1(i1_main), .i2(i2_main), .o1(o1) ); endmodule
VHDL RTL for External Host PR
library ieee; use ieee.std_logic_1164.all; entity top is port( -- PR control block signals pr_clk: in std_logic; pr_request: in std_logic; pr_data: in std_logic_vector(31 downto 0); pr_error: out std_logic; pr_ready: out std_logic; pr_done: out std_logic; -- User signals i1_main: in std_logic; i2_main: in std_logic; o1: out std_logic ); end top; architecture behav of top is component twentynm_prblock is port( clk: in std_logic; corectl: in std_logic; prrequest: in std_logic; data: in std_logic_vector(31 downto 0); error: out std_logic; ready: out std_logic; done: out std_logic ); end component; component pr_v1 is port( i1: in std_logic; i2: in std_logic; o1: out std_logic ); end component; signal pr_gnd : std_logic; begin pr_gnd <= '0'; -- Instantiate the PR control block m_prblock: twentynm_prblock port map ( pr_clk, pr_gnd, pr_request, pr_data, pr_error, pr_ready, pr_done ); -- PR Interface partition pr_inst : pr_v1 port map ( i1_main, i2_main, o1 ); end behav;
2.4. Partial Reconfiguration External Configuration Controller Intel FPGA IP
When using external configuration, you must connect all the top-level ports of the Partial Reconfiguration External Configuration Controller Intel® FPGA IP to the pr_request and status pins, to allow the handshaking of the host with SDM from the Intel® Stratix® 10 or Intel® Agilex™ core. The SDM determines which types of configuration pins to use, according your MSEL setting.
2.4.1. Parameters
The Partial Reconfiguration External Configuration Controller Intel® FPGA IP supports customization of the following parameters.
Parameter |
Value |
Description |
---|---|---|
Enable Busy Interface |
On/Off |
Allows you to Enable or Disable the Busy interface, which asserts a signal to indicate that PR processing is in progress during external configuration. |
2.4.2. Ports
Port Name | Width | Direction | Function |
---|---|---|---|
pr_request | 1 | Input | Indicates that the PR process is ready to begin. The signal is a conduit not synchronous to any clock signal. |
pr_error | 1 | Output | Indicates a partial reconfiguration error. The signal is a conduit not synchronous to any clock signal. |
pr_done | 1 | Output | Indicates that the PR process is complete. The signal is a conduit not synchronous to any clock signal. |
start_addr | 1 | Input | Specifies the start address of PR data in Active Serial Flash. You enable this signal by selecting either Avalon® -ST or Active Serial for the Enable Avalon-ST Pins or Active Serial Pins parameter. The signal is a conduit not synchronous to any clock signal. |
reset | 1 | Input | Active high, synchronous reset signal. |
out_clock | 1 | Output | Clock source that generates from an internal oscillator. |
busy | 1 | Output |
The IP asserts this signal to indicate PR data transfer in progress. You enable this signal by selecting Enable for the Enable busy interface parameter. |
2.4.3. Configuring an External Host for Intel Stratix 10 or Intel Agilex Designs
The external host must respond appropriately to the handshake signals for successful partial reconfiguration. Co-ordinate system-level partial reconfiguration by ensuring that you prepare the correct PR region for partial reconfiguration. After reconfiguration, return the PR region into operating state.
To configure an external host for Intel® Stratix® 10 or Intel® Agilex™ designs, follow these steps:
- Parameterize and generate the Partial Reconfiguration External Configuration Controller Intel FPGA IP, as Generating IP Cores ( Intel Quartus Prime Pro Edition) describes.
- Connect the Partial Reconfiguration External Configuration Controller pr_request, pr_done, and pr_error signals to top-level pins for control and monitor by the external host. You can assign the pin location by clicking Assignments > Pin Planner.
- Click Assignments > Device, and then click the Device & Pin Options button.
- In the Category list, click Configuration.
- For the Configuration scheme, select the scheme that matches with your full device configuration. For example, if your full device configuration uses the AVSTx32 scheme, the PR configuration must use AVSTx32.This option automatically reserves dedicated Avalon® streaming configuration pins for partial reconfiguration during user mode. The pins are exactly same as the Avalon® streaming pins that you use for full device configuration.
The following table describes the PR pins that the external host uses. The PR streaming to Avalon® streaming pins must conform to the Avalon® streaming specification for data transfer with backpressure.
Pin Name | Type | Description |
---|---|---|
pr_request | Input | User-assigned port connected to Partial Reconfiguration External Configuration Controller IP. Logic high on this pin indicates that the PR host is requesting partial reconfiguration. |
pr_done | Output | User-assigned port connected to Partial Reconfiguration External Configuration Controller IP. Logic high on this pin indicates that the partial reconfiguration is complete. |
pr_error | Output | User-assigned port connected to Partial Reconfiguration External Configuration Controller IP. Logic high on this pin indicates an error in the device during partial reconfiguration. |
avst_data: avstx8 - [7:0] avstx16 - [15:0] avstx32 - [31:0] |
Input | These pins provide connectivity for the external host to transfer the PR bitstream to the SDM. The avstx8 data pins are part of the SDM I/O. avstx16 and avstx32 data pins are from I/O 48 bank 3A. |
avst_clk | Input | Clocks the Avalon® streaming interfaces. avst_data and avst_valid are synchronous with avst_clk. The avstx8 clk pin is part of the SDM I/O. avstx16 and avstx32 are from I/O 48 bank 3A. |
avst_valid | Input |
Logic high on this pin indicates the data in avst_data is valid data. The avstx8 data pins are part of the SDM I/O. avstx16 and avstx32 data pins are from I/O 48 bank 3A. |
avst_ready | Output | Logic high on this pin indicates the SDM is ready to accept data from an external host. This output is part of the SDM I/O. |
2.5. Partial Reconfiguration Region Controller Intel FPGA IP
IP Component | Description |
---|---|
Freeze Control and Status Register | Freeze status register that generates the freeze output signal. |
Freeze Control Block | Performs PR handshaking and resets the PR region. |
Conduit Splitter | Connects the controller's freeze signal to one or more Freeze Bridge components. Receives the freeze signal from the Freeze Control Block, and assigns the freeze input signal to one or more freeze output signals. |
Conduit Merger | Connects the illegal_request signal from one or
more Freeze Bridge components to the PR Region Controller. The illegal_request is a single-bit output signal from the Freeze Bridge. Conduit Merger concatenates the single-bit signal from multiple Freeze Bridges into a multi-bit bus. The Conduit Merger then connects the bus to the Freeze Control Block. |
2.5.1. Registers
Name | Address Offset | Access | Description |
---|---|---|---|
freeze_csr_status | 0x00 | Read-Only | Freeze status register. |
csr_ctrl | 0x01 | Read or Write | Control register to enable and disable freeze. |
freeze_illegal_req | 0x02 | Read or Write | High on any bit indicates an illegal request during the freeze state. |
freeze_reg_version | 0x03 | Read-Only | Read-only version register. This register is currently 0xAD000003. |
Bit | Fields | Access | Default Value | Description |
---|---|---|---|---|
31:2 | Reserved | N/A | 0x0 | Reserved bits. Reading these bits always returns zeros. |
1 | unfreeze_status | R | 0 |
Hardware sets this bit to 1 after the PR region returns start_ack to indicate successful start of the persona. Hardware clears this bit to 0 when the unfreeze_req bit is low. This bit is 1 when bridges and other PR region outputs release from reset. |
0 | freeze_status | R | 0 |
Hardware sets this bit to 1 after the PR region returns the stop_ack signal to indicate that the PR region is ready to enter the frozen state Hardware clears this bit to 0 when the freeze_req bit is low. This bit is 0 when bridges and other PR region outputs release from reset. |
Bit | Fields | Access | Default Value | Description |
---|---|---|---|---|
31:3 | Reserved | N/A | 0x0 | Reserved bits. Reading these bits always returns zeros. |
2 | unfreeze_req | R/W | 0 |
Write 1 to this bit to request unfreezing the PR region interfaces. Hardware clears this bit after unfreeze_status is high. Write 0 to this bit to terminate the unfreeze request. Do not assert this bit and the freeze_req bit at the same time. If both freeze_req and unfreeze_req assert at the same time, it is an invalid operation. |
1 | reset_req | R/W | 0 |
Write 1 to start resetting the PR persona. Write 0 to stop resetting the PR persona. |
0 | freeze_req | R/W | 0 |
Write 1 to this bit to start freezing the PR region interfaces.
Hardware clears this bit after freeze_status is high.
Write 0 to this bit to terminate the freeze request if the PR region never returns stop_ack after this bit asserts.
Do not assert this bit and the unfreeze_req bit at the same time. Asserting freeze_req and unfreeze_req simultaneously is an invalid operation. |
Bit | Fields | Access | Default Value | Description |
---|---|---|---|---|
31:n | Reserved | N/A | 0x0 | Reserved bits. Reading these bits always returns zeros. |
n-1:0 | illegal_request | R/W | 0 |
High on any bit of this bus indicates a read or write issue by a static region master when an Avalon® memory-mapped slave freeze bridge is in the freeze state. Identify which freeze bridge has an illegal request by checking each bit on the bus. For example, when illegal_request bit 2 is high, an illegal request occurred in the freeze bridge that connects to interface freeze_conduit_in2 This bus triggers the interrupt signal. Write 1 to clear this bit. n is the number of bridges. |
Bit | Fields | Access | Default Value | Description |
---|---|---|---|---|
31:0 | Version Register | Read-Only | AD000003 | This register bit indicates the CSR register version number. Currently the CSR register is version 0xAD000003. |
2.5.2. Parameters
Parameter |
Value |
Default |
Description |
---|---|---|---|
Enable Avalon® -MM CSR register | On/Off | On |
Enables Avalon® memory-mapped CSR registers in the PR region controller. Disable this option to expose a conduit interface and not instantiate the CSR block. |
Enable interrupt port for illegal request | On/Off | On |
Enables the interrupt port for illegal operations in the PR region controller. |
Number of freeze interfaces | number | Specifies the number of freeze interfaces for freeze operations. You can connect each freeze interface to a freeze bridge or you can use the interface to control other freeze logic. | |
Enable freeze interface without illegal request port | On/Off | Off | Enables creation of additional freeze interface, without the illegal request port. |
Specify the number of freeze interfaces without illegal request port | number | Specifies the number of freeze interfaces without an illegal request port for freeze operations. Only available when you turn on Enable freeze interface without illegal request port. |
2.5.3. Ports
Port | Width | Direction | Description |
---|---|---|---|
clock_clk | 1 | Input | IP core input clock. |
Reset | |||
reset_reset | 1 | Input | Synchronous reset. |
avl_csr_addr | 2 | Input | Avalon® memory-mapped address bus. The address bus is in word addressing. |
avl_csr_read | 1 | Input | Avalon® memory-mapped read control to CSR block. |
avl_csr_write | 1 | Input | Avalon® memory-mapped write control to CSR. |
avl_csr_writedata | 32 | Input | Avalon® memory-mapped write data bus to CSR. |
avl_csr_readdata | 32 | Output | Avalon® memory-mapped read data bus from CSR. |
interrupt_sender_irq | 1 | output | Trigger by illegal read or illegal write. |
Port | Width | Direction | Description |
---|---|---|---|
pr_handshake_stop_req |
1 | Output | An assertion on this output requests that the PR persona stop executing. |
pr_handshake_stop_ack |
1 | Input | A value of 1 on this input acknowledges that the executing PR persona stops executing and a new persona can replace it. |
pr_handshake_start_req |
1 | Output | An assertion on this output requests that the new PR persona starts executing. |
pr_handshake_start_ack |
1 | Input | A value of 1 on this input acknowledges that the new PR persona starts executing and can stop executing on a pr_handshake_stop_req. |
conduit_control_freeze_req | 1 | Input |
Write 1 on this bit to start freezing the PR region interfaces. |
conduit_control_unfreeze_req | 1 | Input | Write 1 on this bit to stop freezing the PR region interfaces. |
conduit_control_freeze_status | 1 | Output | High on this bit indicates that the PR region is successfully goes into freezing state. |
conduit_control_reset | 1 | Input | Write 1 on this bit to reset the PR region. |
conduit_control_unfreeze_status | 1 | Output | High on this bit indicates that the PR region successfully leaves freezing state. |
conduit_control_illegal_req | n | Output | High on this bit indicates illegal data transactions occurring through a Freeze Bridge IP when freeze is active. |
Signal | Width | Direction | Description |
---|---|---|---|
bridge_freeze0_freeze | 1 | Output | This output connects to the freeze input signal of a freeze bridge IP or to control other freeze logic. (Multiple interfaces generate according to the number of freeze interfaces) |
bridge_freeze0_illegal_request | 1 | Input | This input connects to the illegal_request output signal from an instance of the Freeze Bridge IP. |
2.6. Avalon Memory-Mapped Partial Reconfiguration Freeze Bridge IP
Interface Connection | Behavior |
---|---|
Read request to Avalon® memory-mapped slave interface in PR region |
|
Write request to slave interface in PR region |
|
Interface Connection | Behavior |
---|---|
Read/Write request from Avalon® -MM master interface in PR region (old or new persona) |
|
Signal | Avalon® -MM Slave Bridge | Avalon® -MM Master Bridge |
---|---|---|
write | ‘b0 (tie low) | ‘b0 (tie low) |
read | ‘b0 (tie low) | ‘b0 (tie low) |
address | Pass through | Pass through |
writedata | Pass through | Pass through |
readdata | Return <h’DEADBEEF> always | Pass through |
byteenable | Pass through | Pass through |
burstcount | Pass through | Pass through |
beginbursttransfer | ‘b0 (tie low) | ‘b0 (tie low) |
debugaccess | ‘b0 (tie low) | ‘b0 (tie low) |
readdatavalid | Return ‘b1 when there is a request, else ‘b0 | Pass through |
waitrequest | Return ‘b1 when there is a request, else ‘b0 | ‘b0 (tie low) |
response | Return ‘b10 always | Pass through |
lock | ‘b0 (tie low) | ‘b0 (tie low) |
writeresponsevalid | Return ‘b1 when there is a request, else ‘b0 | Pass through |
2.6.1. Parameters
Parameter | Values | Description |
---|---|---|
PR region interface Type | Avalon-MM Slave/Avalon-MM Master | Specifies the interface type for interfacing the PR region with the Freeze Bridge. |
Enable Freeze port from PR region | On/Off | Enables the freeze port that freezes all the outputs of each PR region to a known constant value. Freezing prevents the signal receivers in the static region from receiving undefined signals during the partial reconfiguration process. The freeze of a bridge is the logical OR of this signal from the PR region, and the freeze from the PR region controller. |
Enable the bridge to track unfinished transaction | On/Off | Enables the bridge to track unfinished transactions before freezing the Avalon® interface. Turn on this option when there is no custom logic to stop the Avalon® transaction between the PR region and the static region. If you do not need this feature, disable this option to reduce the size of the IP. |
Enabled Avalon® Interface Signal | Yes/No | Enable (Yes) or disable (No) specific optional Freeze Bridge interface ports. |
Address width | <1-64> | Address width in bits. |
Symbol width | <number> | Data symbol width in bits. The symbol width should be 8 for byte-oriented interfaces. |
Number of symbols | <number> | Number of symbols per word. |
Burstcount width | <number> | The width of the burst count in bits. |
Linewrap burst | On/Off | When On, the address for bursts wraps instead of incrementing. With a wrapping burst, when the address reaches a burst boundary, the address wraps back to the previous burst boundary. Consequently, the IP uses only the low order bits for addressing. |
Constant burst behavior | On/Off | When On, memory bursts are constant. |
Burst on burst boundaries only | On/Off | When On, memory bursts are aligned to the address size. |
Maximum pending reads | <number> | The maximum number of pending reads that the slave can queue. |
Maximum pending writes | <number> | The maximum number of pending writes that the slave can queue. |
Fixed read latency (cycles) | <number> | Sets the read latency for fixed-latency slaves. Not useful on interfaces that include the readdatavalid signal. |
Fixed read wait time (cycles) | <number> | For master interfaces that do not use the waitrequest signal. The read wait time indicates the number of cycles before the master responds to a read. The timing is as if the master asserted waitrequest for this number of cycles. |
Fixed write wait time (cycles) | <number> | For master interfaces that do not use the waitrequest signal. The write wait time indicates the number of cycles before the master accepts a write. |
Address type | WORDS/SYMBOLS | Sets slave interface address type to symbols or words. |
2.6.2. Interface Ports
The Avalon® Memory-Mapped Partial Reconfiguration Freeze Bridge IP core has the following interface ports.
Port |
Width |
Direction |
Description |
---|---|---|---|
clock | 1 | Input | Input clock for the IP. |
reset_n | 1 | Input | Synchronous reset for the IP. |
freeze_conduit_freeze | 1 | Input | When this signal is high, the bridge handles any current transaction properly then freezes the Avalon memory-mapped PR interfaces. |
freeze_conduit_illegal_request | 1 | Output |
High on this bus indicates that an illegal request was issued to the bridge during the freeze state. |
pr_freeze_pr_freeze | 1 | Input | Enabled freeze port coming from the PR region. |
Port |
Width |
Direction |
Description |
---|---|---|---|
slv_bridge_to_pr_read | 1 | Output | Optional Avalon® memory-mapped slave bridge to PR region read port. |
slv_bridge_to_pr_waitrequest | 1 | Input | Optional Avalon® memory-mapped slave bridge to PR region waitrequest port. |
slv_bridge_to_pr_write | 1 | Output | Optional Avalon® memory-mapped slave bridge to PR region write port. |
slv_bridge_to_pr_address | 32 | Output | Optional Avalon® memory-mapped slave bridge to PR region address port. |
slv_bridge_to_pr_byteenable | 4 | Output | Optional Avalon® memory-mapped slave bridge to PR region byteenable port. |
slv_bridge_to_pr_writedata | 32 | Output | Optional Avalon® memory-mapped slave bridge to PR region writedata port. |
slv_bridge_to_pr_readdata | 32 | Input | Optional Avalon® memory-mapped slave bridge to PR region readdata port. |
slv_bridge_to_pr_burstcount | 3 | Output | Optional Avalon® memory-mapped slave bridge to PR region burstcount port. |
slv_bridge_to_pr_readdatavalid | 1 | Input | Optional Avalon® memory-mapped slave bridge to PR region readdatavalid port. |
slv_bridge_to_pr_beginbursttransfer | 1 | Output | Optional Avalon® -MM slave bridge to PR region beginbursttransfer port. |
slv_bridge_to_pr_debugaccess | 1 | Output | Optional Avalon® memory-mapped slave bridge to PR region debugaccess port. |
slv_bridge_to_pr_response | 2 | Input | Optional Avalon® memory-mapped slave bridge to PR region response port. |
slv_bridge_to_pr_lock | 1 | Output | Optional Avalon® -MM slave bridge to PR region lock port. |
slv_bridge_to_pr_writeresponsevalid | 1 | Input | Optional Avalon® memory-mapped slave bridge to PR region writeresponsevalid port. |
Port |
Width |
Direction |
Description |
---|---|---|---|
slv_bridge_to_sr_read | 1 | Input | Avalon® memory-mapped slave bridge to static region read port. |
slv_bridge_to_sr_waitrequest | 1 | Output | Avalon® memory-mapped slave bridge to static region waitrequest port. |
slv_bridge_to_sr_write | 1 | Input | Avalon® memory-mapped slave bridge to static region write port. |
slv_bridge_to_sr_address | 32 | Input | Avalon® memory-mapped slave bridge to static region address port. |
slv_bridge_to_sr_byteenable | 4 | Input | Avalon® memory-mapped slave bridge to static region byteenable port. |
slv_bridge_to_sr_writedata | 32 | Input | Avalon® memory-mapped slave bridge to static region writedata port. |
slv_bridge_to_sr_readdata | 32 | Output | Avalon® memory-mapped slave bridge to static region readdata port. |
slv_bridge_to_sr_burstcount | 3 | Input | Avalon® memory-mapped slave bridge to static region burstcount port. |
slv_bridge_to_sr_beginbursttransfer | 1 | Input | Avalon® memory-mapped slave bridge to static region beginbursttransfer port. |
slv_bridge_to_sr_debugaccess | 1 | Input | Avalon® -MM slave bridge to static region debugaccess port. |
slv_bridge_to_sr_response | 2 | Output | Avalon® memory-mapped slave bridge to static region response port. |
slv_bridge_to_sr_lock | 1 | Input | Avalon® memory-mapped slave bridge to static region lock port. |
slv_bridge_to_sr_writeresponsevalid | 1 | Output | Avalon® memory-mapped slave bridge to static region writereponsevalid port. |
Port |
Width |
Direction |
Description |
---|---|---|---|
mst_bridge_to_pr_read | 1 | Input | Optional Avalon® memory-mapped master bridge to PR region read port. |
mst_bridge_to_pr_waitrequest | 1 | Output | Optional Avalon® memory-mapped master bridge to PR region waitrequest port. |
mst_bridge_to_pr_write | 1 | Input | Optional Avalon® memory-mapped master bridge to PR region write port. |
mst_bridge_to_pr_address | 32 | Input | Optional Avalon® memory-mapped master bridge to PR region address port. |
mst_bridge_to_pr_byteenable | 4 | Input | Optional Avalon® -MM master bridge to PR region byteenable port. |
mst_bridge_to_pr_writedata | 32 | Input | Optional Avalon® -MM master bridge to PR region writedata port. |
mst_bridge_to_pr_readdata | 32 | Output | Optional Avalon® memory-mapped master bridge to PR region readdata port. |
mst_bridge_to_pr_burstcount | 3 | Input | Optional Avalon® memory-mapped master bridge to PR region burstcount port. |
mst_bridge_to_pr_readdatavalid | 1 | Output | Optional Avalon® memory-mapped master bridge to PR region readdatavalid port. |
mst_bridge_to_pr_beginbursttransfer | 1 | Input | Optional Avalon® memory-mapped master bridge to PR region beginbursttransfer port. |
mst_bridge_to_pr_debugaccess | 1 | Input | Optional Avalon® memory-mapped master bridge to PR region debugaccess port. |
mst_bridge_to_pr_response | 2 | Output | Optional Avalon® memory-mapped master bridge to PR region response port. |
mst_bridge_to_pr_lock | 1 | Input | Optional Avalon® memory-mapped master bridge to PR region lock port. |
mst_bridge_to_pr_writeresponsevalid | 1 | Output | Optional Avalon® memory-mapped master bridge to PR region writeresponsevalid port. |
Port |
Width |
Direction |
Description |
---|---|---|---|
mst_bridge_to_sr_read | 1 | Output | Avalon® memory-mapped master bridge to static region read port. |
mst_bridge_to_sr_waitrequest | 1 | Input | Avalon® memory-mapped bridge to static region waitrequest port. |
mst_bridge_to_sr_write | 1 | Output | Avalon® memory-mapped master bridge to static region write port. |
mst_bridge_to_sr_address | 32 | Output | Avalon® memory-mapped master bridge to static region address port. |
mst_bridge_to_sr_byteenable | 4 | Output | Avalon® memory-mapped master bridge to static region byteenable port. |
mst_bridge_to_sr_writedata | 32 | Output | Avalon® memory-mapped master bridge to static region writedata port. |
mst_bridge_to_sr_readdata | 32 | Input | Avalon® memory-mapped master bridge to static region readdata port. |
mst_bridge_to_sr_burstcount | 3 | Output | Avalon® memory-mapped master bridge to static region burstcount port. |
mst_bridge_to_sr_readdatavalid | 1 | Input | Avalon® memory-mapped master bridge to static region readdatavalid port. |
mst_bridge_to_sr_beginbursttransfer | 1 | Output | Avalon® memory-mapped master bridge to static region beginbursttransfer port. |
mst_bridge_to_sr_debugaccess | 1 | Output | Avalon® memory-mapped master bridge to static region debugaccess port. |
mst_bridge_to_sr_response | 2 | Input | Avalon® memory-mapped master bridge to static region response port. |
mst_bridge_to_sr_lock | 1 | Output | Avalon® memory-mapped master bridge to static region lock port. |
mst_bridge_to_sr_writeresponsevalid | 1 | Input | Avalon® memory-mapped master bridge to static region writeresponsevalid port. |
2.7. Avalon Streaming Partial Reconfiguration Freeze Bridge IP
Interface Type | Behavior |
---|---|
Source interface in the PR region with packet transfer (old or new persona) |
|
Source interface in the PR region without packet transfer (old or new persona) | When the freeze signal is high, the Freeze Bridge does not send transactions to the static region. The Freeze Bridge remains idle until the bridge leaves the frozen state. |
Source interface in the PR region with max_channel > 1 (old or new persona) | When multiple channels transfer unfinished transactions, the Freeze Bridge tracks the channel values to ensure that all packet transactions from different channels end by asserting the endofpacket bit during the frozen state. |
Source interface in the PR region with ready_latency > 0 (old or new persona) | When the Freeze Bridge drives endofpacket, valid, or channel outputs to the static region, the Freeze Bridge reads the ready_latency value. The ready_latency value defines the actual clock cycle when the sink component is ready for data. |
Interface Type | Behavior |
---|---|
Sink interface in PR region |
For transactions that includes packet transfers, when the freeze signal goes high, the Freeze Bridge holds the ready signal high to the static region source until any unfinished transaction completes. For transactions that do not include packet transfers, when the freeze signal goes high, the Freeze Bridge holds the ready signal low during the freeze period. The illegal_request signal asserts high to indicate that the current transaction is an error. Configure the design to stop sending transactions to the PR region after the illegal_request signal is high. |
Sink interface in PR region with ready_latency > 0 | When the Freeze Bridge drives endofpacket, valid, or channel outputs to the PR region, the Freeze Bridge must observe the ready_latency value. The ready_latency value defines the actual clock cycle when the sink component is ready for data. |
2.7.1. Parameters
Parameter | Values | Description |
---|---|---|
PR region Interface Type | Avalon-ST Source/Avalon-ST Sink | Specifies the interface type for interfacing the PR region with the freeze bridge. |
Enable Freeze port from PR region | On/Off | Enables the freeze port to freeze all the outputs of each PR region to a known constant value. Freezing prevents the signal receivers in the static region from receiving undefined signals during the partial reconfiguration process. |
Select Yes or No to enable or disable interface ports | Yes/No | Enables or disables specific optional freeze bridge interface ports. |
Channel width | <1-128> | Specifies the width of the channel signal. |
Error width | <1-256> | Specifies the width of the error signal. |
Data bits per symbol | <1-512> | Specifies the number of bits per symbol. |
Symbols per beat | <1-512> | Specifies the number of symbols that transfer on every valid clock cycle. |
Error descriptors | <text> | Specifies one or more strings to describe the error condition for each bit of the error port on the sink interface connected to the source interface. Click the plus or minus buttons to add or remove descriptors. |
Max channel number | <0-255> | Specifies the maximum number of output channels. |
Ready latency | <0-8> | Specifies what ready latency to expect from the source interface connected to the sink interface. The ready latency is the number of cycles from the time ready asserts until valid data is driven. |
2.7.2. Ports
Port |
Width |
Direction |
Description |
---|---|---|---|
clock | 1 | Input | Input clock for the IP. |
freeze_conduit_freeze | 1 | Input | When this signal is high, the bridge handles any current transaction properly then freezes the PR interfaces. |
freeze_conduit_illegal_request | 1 | Output |
High on this bus indicates that an illegal request was issued to the bridge during the freeze state. n – number of freeze bridge |
pr_freeze_pr_freeze | 1 | Input | Enabled freeze port from the PR region. |
reset_n | 1 | Input | Synchronous reset for the IP. |
Port |
Width |
Direction |
Description |
---|---|---|---|
sink_bridge_to_sr_channel | 1 | Input | Avalon® streaming sink bridge to static region channel port. |
sink_bridge_to_sr_data | 32 | Input | Avalon® streaming sink bridge to static region data port. |
sink_bridge_to_sr_empty | 2 | Input | Avalon® streaming sink bridge to static region empty port. |
sink_bridge_to_sr_error | 1 | Input | Avalon® streaming sink bridge to static region error port. |
sink_bridge_to_sr_ready | 1 | Output | Avalon® streaming sink bridge to static region ready port. |
sink_bridge_to_sr_valid | 1 | Input | Avalon® streaming sink bridge to static region valid port. |
sink_bridge_to_sr_endofpacket | 1 | Input | Avalon® streaming sink bridge to static region endofpacket port. |
sink_bridge_to_sr_startofpacket | 1 | Input | Avalon® streaming sink bridge to static region startofpacket port. |
Port |
Width |
Direction |
Description |
---|---|---|---|
sink_bridge_to_pr_channel | 1 | Output | Optional Avalon® streaming sink bridge to PR region channel port. |
sink_bridge_to_pr_data | 32 | Output | Optional Avalon® streaming sink bridge to PR region data port. |
sink_bridge_to_pr_empty | 2 | Output | Optional Avalon® streaming sink bridge to PR region empty port. |
sink_bridge_to_pr_error | 1 | Output | Optional Avalon® streaming sink bridge to PR region error port. |
sink_bridge_to_pr_ready | 1 | Input | Optional Avalon® -ST sink bridge to PR region ready port. |
sink_bridge_to_pr_valid | 1 | Output | Optional Avalon® streaming sink bridge to PR region valid port. |
sink_bridge_to_pr_endofpacket | 1 | Output | Optional Avalon® streaming sink bridge to PR region endofpacket port. |
sink_bridge_to_pr_startofpacket | 1 | Output | Optional Avalon® streaming sink bridge to PR region startofpacket port. |
Port |
Width |
Direction |
Description |
---|---|---|---|
source_bridge_to_sr_channel | 1 | Output | Avalon® streaming source bridge to static region channel port. |
source_bridge_to_sr_data | 32 | Output | Avalon® streaming source bridge to static region data port. |
source_bridge_to_sr_empty | 2 | Output | Avalon® streaming source bridge to static region empty port. |
source_bridge_to_sr_error | 1 | Output | Avalon® streaming source bridge to static region error port. |
source_bridge_to_sr_ready | 1 | Input | Avalon® streaming source bridge to static region ready port. |
source_bridge_to_sr_valid | 1 | Output | Avalon® streaming source bridge to static region valid port. |
source_bridge_to_sr_endofpacket | 1 | Output | Avalon® streaming source bridge to static region endofpacket port. |
source_bridge_to_sr_startofpacket | 1 | Output | Avalon® streaming source bridge to static region startofpacket port. |
Port |
Width |
Direction |
Description |
---|---|---|---|
source_bridge_to_pr_channel | 1 | Input | Optional Avalon® streaming source bridge to PR region channel port. |
source_bridge_to_pr_data | 32 | Input | Optional Avalon® streaming source bridge to PR region data port. |
source_bridge_to_pr_empty | 2 | Input | Optional Avalon® streaming source bridge to PR region empty port. |
source_bridge_to_pr_error | 1 | Input | Optional Avalon® -ST source bridge to PR region error port. |
source_bridge_to_pr_ready | 1 | Output | Optional Avalon® streaming source bridge to PR region ready port. |
source_bridge_to_pr_valid | 1 | Input | Optional Avalon® streaming source bridge to PR region valid port. |
source_bridge_to_pr_endofpacket | 1 | Input | Optional Avalon® streaming source bridge to PR region endofpacket port. |
source_bridge_to_pr_startofpacket | 1 | Input | Optional Avalon® streaming source bridge to PR region startofpacket port. |
2.8. Generating and Simulating Intel FPGA IP
2.8.1. Generating IP Cores ( Intel Quartus Prime Pro Edition)
Follow these steps to locate, instantiate, and customize an IP core in the parameter editor:
- Create or open an Intel® Quartus® Prime project (.qpf) to contain the instantiated IP variation.
- In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize. To locate a specific component, type some or all of the component’s name in the IP Catalog search box. The New IP Variation window appears.
-
Specify a top-level name for your custom IP variation. Do not
include spaces in IP variation names or paths. The parameter editor saves the IP
variation settings in a file named
<your_ip>
.ip. Click OK. The parameter editor appears.
Figure 72. IP Parameter Editor ( Intel® Quartus® Prime Pro Edition)
-
Set the parameter values in the parameter editor and view the
block diagram for the component. The Parameterization Messages tab at the bottom displays any errors
in IP parameters:
- Optionally, select preset parameter values if provided for your IP core. Presets specify initial parameter values for specific applications.
- Specify parameters defining the IP core functionality, port configurations, and device-specific features.
- Specify options for processing the IP core files in other EDA tools.
Note: Refer to your IP core user guide for information about specific IP core parameters. - Click Generate HDL. The Generation dialog box appears.
- Specify output file generation options, and then click Generate. The synthesis and simulation files generate according to your specifications.
- To generate a simulation testbench, click Generate > Generate Testbench System. Specify testbench generation options, and then click Generate.
- To generate an HDL instantiation template that you can copy and paste into your text editor, click Generate > Show Instantiation Template.
- Click Finish. Click Yes if prompted to add files representing the IP variation to your project.
-
After generating
and instantiating your IP variation, make appropriate pin assignments to
connect ports.
Note: Some IP cores generate different HDL implementations according to the IP core parameters. The underlying RTL of these IP cores contains a unique hash code that prevents module name collisions between different variations of the IP core. This unique code remains consistent, given the same IP settings and software version during IP generation. This unique code can change if you edit the IP core's parameters or upgrade the IP core version. To avoid dependency on these unique codes in your simulation environment, refer to Generating a Combined Simulator Setup Script.
2.8.2. Running the Freeze Bridge Update script
Running this script updates the master and slave interfaces or the sink and source interfaces of the Freeze Bridge, according to the Avalon® property settings of the connecting PR region component.
To run the Update Freeze Bridge Parameters script:
- Open a Platform Designer system containing one or more instances of the Freeze Bridge component.
- In Platform Designer, click View > System Scripting. The System Scripting tab displays Platform Designer Built-in Scripts.
- To update all freeze bridges in your Platform Designer system, set update_all_freeze_bridges to 1 in the Additional Commands section of the script. To update only a single freeze bridge, click the freeze bridge instance.
-
Click Run Script. The script runs and updates the freeze
bridge parameters.
Figure 73. Platform Designer System Scripting Tab
2.8.3. IP Core Generation Output ( Intel Quartus Prime Pro Edition)
File Name | Description |
---|---|
<your_ip>.ip | Top-level IP variation file that contains the parameterization of an IP core in your project. If the IP variation is part of a Platform Designer system, the parameter editor also generates a .qsys file. |
<your_ip>.cmp | The VHDL Component Declaration (.cmp) file is a text file that contains local generic and port definitions that you use in VHDL design files. |
<your_ip>_generation.rpt | IP or Platform Designer generation log file. Displays a summary of the messages during IP generation. |
<your_ip>.qgsimc (Platform Designer systems only) | Simulation caching file that compares the .qsys and .ip files with the current parameterization of the Platform Designer system and IP core. This comparison determines if Platform Designer can skip regeneration of the HDL. |
<your_ip>.qgsynth (Platform Designer systems only) | Synthesis caching file that compares the .qsys and .ip files with the current parameterization of the Platform Designer system and IP core. This comparison determines if Platform Designer can skip regeneration of the HDL. |
<your_ip>.csv | Contains information about the upgrade status of the IP component. |
<your_ip>.bsf | A symbol representation of the IP variation for use in Block Diagram Files (.bdf). |
<your_ip>.spd | Input file that ip-make-simscript requires to generate simulation scripts. The .spd file contains a list of files you generate for simulation, along with information about memories that you initialize. |
<your_ip>.ppf | The Pin Planner File (.ppf) stores the port and node assignments for IP components you create for use with the Pin Planner. |
<your_ip>_bb.v | Use the Verilog blackbox (_bb.v) file as an empty module declaration for use as a blackbox. |
<your_ip>_inst.v or _inst.vhd | HDL example instantiation template. Copy and paste the contents of this file into your HDL file to instantiate the IP variation. |
<your_ip>.regmap | If the IP contains register information, the Intel® Quartus® Prime software generates the .regmap file. The .regmap file describes the register map information of master and slave interfaces. This file complements the .sopcinfo file by providing more detailed register information about the system. This file enables register display views and user customizable statistics in System Console. |
<your_ip>.svd |
Allows HPS System Debug tools to view the register maps of peripherals that connect to HPS within a Platform Designer system. During synthesis, the Intel® Quartus® Prime software stores the .svd files for slave interface visible to the System Console masters in the .sof file in the debug session. System Console reads this section, which Platform Designer queries for register map information. For system slaves, Platform Designer accesses the registers by name. |
<your_ip>.v <your_ip>.vhd |
HDL files that instantiate each submodule or child IP core for synthesis or simulation. |
mentor/ | Contains a msim_setup.tcl script to set up and run a ModelSim* simulation. |
aldec/ | Contains a Riviera-PRO* script rivierapro_setup.tcl to setup and run a simulation. |
/synopsys/vcs /synopsys/vcsmx |
Contains a shell script vcs_setup.sh to set up and run a VCS* simulation. Contains a shell script vcsmx_setup.sh and synopsys_sim.setup file to set up and run a VCS* MX simulation. |
/cadence | Contains a shell script ncsim_setup.sh and other setup files to set up and run an NCSim simulation. |
/xcelium | Contains an Xcelium* Parallel simulator shell script xcelium_setup.sh and other setup files to set up and run a simulation. |
/submodules | Contains HDL files for the IP core submodule. |
<IP submodule>/ | Platform Designer generates /synth and /sim sub-directories for each IP submodule directory that Platform Designer generates. |
2.8.4. Intel Arria 10 and Intel Cyclone 10 GX PR Control Block Simulation Model
The Intel® Arria® 10 and Intel® Cyclone® 10 GX PR control blocks support PR simulation. Sending a simulation RBF (PR bitstream) allows the PR control block to behave accordingly, to PR simulation success or PR simulation failure. To activate simulation of a specific PR persona in your PR region simulation wrapper, use a PR ID encoded in the simulation RBF, in conjunction with the PR control block. Simulate the PR control block either as standalone, or as part of the simulation file set for the Partial Reconfiguration Controller IP core.
The PR control block simulation model contains two additional simulation-only ports—sim_state and sim_pr_id. Connect these simulation ports, and the other ports, to the twentynm_prblock_if SystemVerilog interface. This connection allows monitoring of the PR control block using your testbench’s PR control block monitor. The Intel® Quartus® Prime software automatically instantiates the twentynm_prblock_if interface when generating the simulation file set of the Partial Reconfiguration IP core. Obtain a reference to the twentynm_prblock_if that the IP instantiates by using the alt_pr_test_pkg::twentynm_prblock_if_mgr singleton, as shown in the following example:
virtual twentynm_prblock_if prblock_if; alt_pr_test_pkg::twentynm_prblock_if_mgr cb_mgr; // Get the PR control block from the prblock manager cb_mgr = alt_pr_test_pkg::twentynm_prblock_if_mgr::get(); prblock_if = cb_mgr.if_ref;
interface twentynm_prblock_if(input logic pr_clk, input logic clk); logic prrequest; logic [31:0] data; wire error; wire ready; wire done; logic [31:0] sim_only_state; wire [31:0] sim_only_pr_id; // All signals are async except data clocking cb1 @(posedge pr_clk); output data; endclocking endinterface : twentynm_prblock_ifFor more information on the twentynm_prblock_if interface, refer to the <installation directory> /eda/sim_lib/altera_lnsim.sv file.
package twentynm_prblock_test_pkg; typedef enum logic [31:0] { NONE, IDLE, PR_REQUEST, PR_IN_PROGRESS, PR_COMPLETE_SUCCESS, PR_COMPLETE_ERROR, PR_INCOMPLETE_EARLY_WITHDRAWL, PR_INCOMPLETE_LATE_WITHDRAWL } PR_EVENT_TYPE;
When the simulation state is PR_IN_PROGRESS, the affected PR region must have its simulation output multiplexes driven to X, by asserting the pr_activate signal. This action simulates the unknown outputs of the PR region during partial reconfiguration. In addition, you must assert the pr_activate signal in the PR simulation model to load all registers in the PR model with the PR activation value.
Once the simulation state reaches PR_COMPLETE_SUCCESS, activate the appropriate PR persona using the appropriate PR region simulation wrapper mux sel signals. You can decode the region, as well as the specific select signal from the sim_only_pr_id signal of the PR control block. This ID corresponds to the encoded ID in the simulation RBF.
1 | zero padding blocks | 0x00000000 |
2 | PR_HEADER_WORD | 0x0000A65C |
3 | PR_ID | 32-bit user ID |
4 | PRDATA_COUNT_0 | 0x01234567 |
5 | PRDATA_COUNT_1 | 0x89ABCDEF |
6 | PRDATA_COUNT_2 | 0x02468ACE |
7 | PRDATA_COUNT_3 | 0x13579BDF |
2.8.5. Generating the PR Persona Simulation Model
When using the PR simulation model for the persona, the netlist includes a new altera_sim_pr_activate top-level signal for the model. You can asynchronously drive this signal to load all registers in the model with X. This feature allows you to verify the reset sequence of the new persona on PR event completion. Verify the reset sequence through inspection, using SystemVerilog assertions, or using other checkers.
By default, the PR simulation model asynchronously loads X into the register’s storage element on pr_activate signal assertion. You can parameterize this behavior on a per register basis, or on a simulation-wide default basis. The simulation model supports four built-in modes:
- load X
- load 1
- load 0
- load rand
Specify these modes using the SystemVerilog classes:
- dffeas_pr_load_x
- dffeas_load_1
- dffeas_load_0
- dffeas_load_rand
Optionally, you can create your own PR activation class, where your class must define the pr_load variable to specify the PR activation value.
Follow these steps to generate the simulation model for a PR design:
-
Open the base revision of a PR project in
Intel®
Quartus® Prime Pro Edition, and then click Processing > Start > Start Analysis & Synthesis. Alternatively, run this command-line equivalent:
quartus_syn <project name> -c <base revision name>
-
After synthesis is complete, click Project > Export Design Partition, and then select the root partition
for the Partition name, and select synthesized for the Snapshot. Click OK. Alternatively,
run this command-line equivalent:
quartus_cdb <project name> -c <base revision name> \ "--export_block root_partition --snapshot synthesized \ --file <static qdb name>
- Click Project > Revisions and switch the current revision to that of the persona you want to export.
-
Click Processing > Start > Start Analysis & Synthesis. Alternatively, run this command-line equivalent:
quartus_syn <project name> -c <persona revision name>
-
After synthesis of the persona revision completes, execute the
following at the command line to generate the PR simulation model:
quartus_eda <project name> –c <persona revision name> "--pr --simulation \ --tool=modelsim --format=verilog --partition=<pr partition name> \ --module=<partition name>=<persona module name>
- Repeat steps 3 through 5 for all personas that you want to simulate.
Complete PR Simulation Model Generation Script
quartus_syn <project name> -c <base revision name> quartus_cdb <project name> -c <base revision name> \ "--export_block root_partition --snapshot synthesized \ --file <static qdb name> quartus_syn <project name> -c <persona revision name> quartus_eda <project name> –c <persona revision name> \ "--pr --simulation --tool=modelsim --format=verilog \ --partition=<pr partition name> --module=<partition name>=\ <persona module name>
You can use the PR mode of the EDA netlist writer to generate the gate level netlist of a PR region. Refer to the "EDA Netlist Writer and Gate Level-Netlists" section of the Intel® Quartus® Prime Pro Edition User Guide: Third Party Simulation.
2.9. Intel Quartus Prime Pro Edition User Guide: Partial Reconfiguration Archive
Intel® Quartus® Prime Version | User Guide |
---|---|
20.2 | Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration |
20.1 | Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration |
19.4 | Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration |
19.3 | Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration |
19.1 | Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration |
18.1 | Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration |
18.0 | Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration |
2.10. Partial Reconfiguration Solutions IP User Guide Revision History
Document Version | Intel® Quartus® Prime Version | Changes |
---|---|---|
2020.09.28 | 20.3 |
|
2020.08.07 | 20.2 |
|
2019.12.16 | 19.4.0 |
|
2019.09.30 | 19.3.0 |
|
2019.06.07 | 19.1.0 |
|
2019.04.22 | 19.1.0 |
|
2019.01.04 | 18.1.0 |
|
2018.12.07 | 18.1.0 |
|
2018.09.24 | 18.1.0 |
|
2018.06.27 | 18.0.0 | Updated freeze_status signal description in Registers: Partial Reconfiguration Region Controller . |
2018.06.18 | 18.0.0 |
|
2018.05.07 | 18.0.0 |
|
2017.11.06 | 17.1.0 |
|
2017.05.08 | 17.0.0 | Initial public release. |
A. Intel Quartus Prime Pro Edition User Guides
Refer to the following user guides for comprehensive information on all phases of the Intel® Quartus® Prime Pro Edition FPGA design flow.