Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

ID 683834
Date 4/01/2024
Document Table of Contents

1.5. External Host Partial Reconfiguration

In external host control, an external FPGA or CPU controls the PR configuration using external dedicated PR pins on the target device. When using an external host, you must implement the control logic for transmission of the bitstream to the hard FPGA programming pins.
Figure 5. PR System Using an External Host ( Arria® 10 Example)