Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

ID 683834
Date 4/01/2024
Document Table of Contents

1.4. Internal Host Partial Reconfiguration

With internal host control, an internal controller, a Nios® II processor, or an interface such as PCI Express* ( PCIe* ) or Ethernet, communicates directly with the Arria® 10 or Cyclone® 10 GX PR control block, or with the SDM in Agilex® 7, Agilex™ 5, and Stratix® 10 devices.

To transfer the PR bitstream into the PR control block or SDM, you use the Avalon® memory-mapped interface on the Partial Reconfiguration Controller IP core. When the device enters user mode, you initiate partial reconfiguration through the FPGA core fabric using the PR internal host.
Note: If you create your own control logic for the PR host, the logic must meet the PR interface requirements.
Figure 3. Internal Host PR

When performing partial reconfiguration with an internal host, use the dedicated PR pins (PR_REQUEST, PR_READY, PR_DONE, and PR_ERROR) as regular I/Os. Implement your static region logic to retrieve the PR programming bitstreams from an external memory, for processing by the internal host.

Figure 4.  Arria® 10 FPGA System Using an Internal PR Host Example

For example, send the programming bitstreams for partial reconfiguration through the PCI Express* link. Then, you process the bitstreams with your PR control logic and send the bitstreams to the PR IP core for programming. nCONFIG moves the device out of the user mode into the device configuration mode.1

1 nCONFIG can lock the device and force a power-cycle. PR programming may corrupt the static logic, due to improper use, causing disconnection of the core clock input to configuration block and unresponsive configuration. You must reset the PR IP before toggling nCONFIG.