Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

ID 683834
Date 4/01/2024
Document Table of Contents

2.3.8. PR Control Block and CRC Block VHDL Manual Instantiation

The following example shows manual instantiation of a PR control block inside your top-level Arria® 10 project, Chip_Top, in VHDL:

module Chip_Top is port (
 --User I/O signals (excluding signals that relate to PR)
-- Following shows the connectivity within the Chip_Top module
Core_Top : Core_Top
 port_map (
m_pr : twentynm_prblock
 port map(
clk => dclk,
 corectl =>'1', --1 - when using PR from inside
 --0 - for PR from pins; You must also enable
 -- the appropriate option in Quartus Prime settings
 prrequest => pr_request,
 data => pr_data,
 error => pr_error,
 ready => pr_ready,
 done => pr_done
m_crc : twentynm_crcblock
 port map(
 shiftnld => '1', --If you want to read the EMR register when
 clk => dummy_clk, --error occurrs, refer to AN539 for the
 --connectivity for this signal. If you only want
 --to detect CRC errors, but plan to take no
 --further action, you can tie the shiftnld
 --signal to logical high.
 crcerror => crc_error
Note: You are not required to connect a real clock source to dummy_clk, but you must connect dummy_clk to an I/O pin to avoid removal of this signal.