Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

ID 683834
Date 4/01/2024
Document Table of Contents

2.2. Partial Reconfiguration Controller Intel FPGA IP

The Partial Reconfiguration Controller Intel® FPGA IP provides partial reconfiguration functionality for Stratix® 10 and Agilex® 7 designs. The IP core provides a standard interface to the FPGA secure device manager (SDM), and has a maximum clock frequency of 200 MHz.
Figure 41. Partial Reconfiguration Controller Avalon® Streaming Interface ( Agilex® 7, Agilex™ 5, and Stratix® 10 Designs)
Note: If an error occurs during PR operation for an Agilex® 7, Agilex™ 5, or Stratix® 10 design using SEU detection, the PR region is frozen, becomes non-functional, and SEU detection is disabled for all sectors within the PR region and certain sectors adjacent to PR region. To resolve this error and restore SEU detection on affected areas, perform a full chip configuration.
5 Avalon memory mapped interface variant also available.