Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

ID 683834
Date 4/01/2024
Document Table of Contents

2.2.4. Timing Specifications

The following timing diagram illustrates a successful PR operation with the Partial Reconfiguration Controller Intel® FPGA IP. The status[2:0] output signal indicates whether the operation passes or fails. The PR operation initiates upon assertion of the pr_start signal. Monitor the status[] signal to detect the end of the PR operation.
Figure 45.  Timing Specifications