Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

ID 683834
Date 4/01/2024
Document Table of Contents

1.6.1. Step 1: Identify Partial Reconfiguration Resources

When designing for partial reconfiguration, you must first determine the logical hierarchy boundaries that you can define as reconfigurable partitions. Reconfigurable partitions must contain only core resources, such as LABs, embedded memory blocks (M20Ks and MLABs), and DSP blocks in the FPGA.

All periphery resources, such as transceivers, external memory interfaces, GPIOs, I/O receivers, and the hard processor system (HPS), must be in the static region. Partial reconfiguration of global network buffers for clocks and resets is not possible.

Table 2.  Supported Reconfiguration Methods
Hardware Resource Block Reconfiguration Method
Logic Block Partial reconfiguration
Digital Signal Processing Partial reconfiguration
Memory Block Partial reconfiguration
Core Routing Partial reconfiguration
Transceivers/PLL Dynamic reconfiguration
I/O Blocks Not supported
Clock Control Blocks Not supported

After identifying the resources for PR, set up the design hierarchy and source code to support this partitioning. Refer to Partial Reconfiguration Design Considerations.