25G Ethernet Intel® FPGA IP

This IP core implements the 25G and 50G Ethernet Specification, Draft 1.4 from the 25 Gigabit Ethernet Consortium. The IP core includes an option to support unidirectional transport as defined in Clause 66 of the IEEE 802.3-2012 Ethernet Standard. The media access control (MAC) client side interface for the 25GbE IP core is a 64 bit Avalon® streaming interface (Avalon-ST). It maps to one 25.78125 Gbps transceiver. The IP core optionally includes Reed-Solomon forward error correction (FEC) for support of direct attach copper (DAC) cable.

Read the 25G Ethernet Intel® Arria® 10 FPGA IP user guide ›

Read the 25G Ethernet Intel® Stratix® 10 FPGA IP user guide ›

Read the 25G Ethernet Intel® Arria® 10 FPGA IP design example user guide ›

Read the 25G Ethernet Intel® Stratix® 10 FPGA IP design example user guide ›

25G Ethernet Intel® FPGA IP

The 25G Ethernet Intel FPGA IP core with various optional features is also available as hard IP on Intel® Stratix® 10 devices with E-Tiles. More details can be found on the E-Tile Hard IP for Ethernet page.

Features

PHY:

  • Soft PCS logic that interfaces seamlessly to Intel® Stratix® 10 FPGA 25.78125 gigabits per second (Gbps) or 10.3125 Gbps serial transceivers.
  • Support for dynamic reconfiguration between the Ethernet data rates of 25.78125 Gbps and 10.3125 Gbps.
  • Optional Reed-Solomon forward error correction (FEC).

Frame structure control:

  • Support for jumbo packets, defined as packets greater than 1500 bytes.
  • Receive (RX) CRC removal and pass-through control.
  • Transmit (TX) CRC generation and insertion.
  • RX and TX preamble pass-through option for applications that require proprietary user management information transfer.
  • TX automatic frame padding to meet the 64-byte minimum Ethernet frame length.

Frame monitoring and statistics:

  • RX CRC checking and error reporting.
  • RX malformed packet checking per IEEE specification.
  • Optional statistics counters.
  • Optional fault signaling detects and reports local fault and generates remote fault, with IEEE 802.3ba-2012 Ethernet Standard Clause 66 support.
  • Unidirectional transport as defined in Clause 66 of the IEEE 802.3-2012 Ethernet Standard.

Flow Control:

  • Standard IEEE 802.3 Clause 31 and Priority-Based IEEE 802.1Qbb flow control.

Precision time protocol support:

  • Optional support for the IEEE Standard 1588-2008 Precision Clock Synchronization Protocol (1588 PTP). This feature supports PHY operating speed with a constant timestamp accuracy of ± 3 ns and a dynamic timestamp accuracy of ± 1 ns.

Debug and testability:

  • Programmable serial PMA local loopback (TX to RX) at the serial transceiver for self-diagnostic testing.
  • TX error insertion capability.
  • Optional access to Altera Debug Master Endpoint (ADME) for serial link debugging or monitoring PHY signal integrity.

User system interfaces:

  • Avalon® Memory-Mapped (Avalon-MM) management interface to access the IP core control and status registers.
  • Avalon® Streaming (Avalon-ST) data path interface connects to client logic.
  • Configurable ready latency of 0 or 3 clock cycles for Avalon-ST TX interface.
  • Hardware and software reset control.

IP Status

 

Status

Production
Ordering Codes

25G Ethernet Intel® FPGA IP

IP-25GEUMACPHY (Arria® 10)
IP-25GEUMACPHY (Intel® Stratix® 10) – No FEC, No PTP support
IP-25GEUMACPHYF (Intel® Stratix® 10) – No FEC, With PTP support
IP-25GEUMACPHYFC (Intel® Stratix® 10) – With FEC, No PTP support
IP-25GEUMACPHYFFC (Intel® Stratix® 10) – With FEC, With PTP support
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