25G Ethernet Intel® Arria® 10 FPGA IP Design Example User Guide

ID 683833
Date 12/14/2020
Public
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1. 25G Ethernet Intel FPGA IP Quick Start Guide

Updated for:
Intel® Quartus® Prime Design Suite 20.4
IP Version 19.4.1

The 25G Ethernet Intel FPGA IP core provides a simulation testbench and a hardware design example that supports compilation and hardware testing. When you generate the design example, the parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware. You can download the compiled hardware design to an Intel® Arria® 10 GT device.

Note: This design example targets the Intel® Arria® 10 GT device and requires a 25G retimer. Please contact your Intel FPGA representative to inquire about a platform suitable to run this hardware example. In some cases a loan of appropriate hardware may be available.

In addition, Intel provides a compilation-only example project that you can use to quickly estimate IP core area and timing.

Figure 1. Design Example Usage

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