1. 25G Ethernet Intel FPGA IP Quick Start Guide
|Intel® Quartus® Prime Design Suite 20.4|
|IP Version 19.4.1|
The 25G Ethernet Intel FPGA IP core provides a simulation testbench and a hardware design example that supports compilation and hardware testing. When you generate the design example, the parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware. You can download the compiled hardware design to an Intel® Arria® 10 GT device.
In addition, Intel provides a compilation-only example project that you can use to quickly estimate IP core area and timing.
Did you find the information on this page useful?