25G Ethernet Intel® Arria® 10 FPGA IP Design Example User Guide

ID 683833
Date 12/14/2020

2.3. 25G Ethernet Intel FPGA IP Design Example Registers

Table 5.   25G Ethernet Intel FPGA IP Hardware Design Example Register MapLists the memory mapped register ranges for the hardware design example. You access these registers with the reg_read and reg_write functions in the System Console.

Word Offset

Register Category


25G Ethernet Intel FPGA IP core registers.


Intel® Arria® 10 dynamic reconfiguration registers. Register base address is 0x4000.