25G Ethernet Intel® Arria® 10 FPGA IP Design Example User Guide

ID 683833
Date 12/14/2020
Public

1.6. Compiling and Configuring the Design Example in Hardware

To compile the hardware design example and configure it on your Intel® Arria® 10 GT device, follow these steps:

  1. Ensure hardware design example generation is complete.
  2. In the Intel® Quartus® Prime software, open the Intel® Quartus® Prime project <design_example_dir>/hardware_test_design/eth_ex_25g.qpf.
  3. Before compiling, ensure you have implemented the workaround from the KDB Answer How do I compensate for the jitter of PLL cascading or non-dedicated clock path for Arria 10 PLL reference clock? if relevant for your software release.
  4. On the Processing menu, click Start Compilation.
  5. After you generate a SRAM object file .sof, follow these steps to program the hardware design example on the Intel® Arria® 10 device:
    1. On the Tools menu, click Programmer.
    2. In the Programmer, click Hardware Setup.
    3. Select a programming device.
    4. Select and add the Intel® Arria® 10 GT board with 25G retimer to your Intel® Quartus® Prime session.
    5. Ensure that Mode is set to JTAG.
    6. Select the Intel® Arria® 10 device and click Add Device. The Programmer displays a block diagram of the connections between the devices on your board.
    7. In the row with your .sof, check the box for the .sof.
    8. Check the box in the Program/Configure column.
    9. Click Start.
Note: This design example targets the Intel® Arria® 10 GT device. Please contact your Intel FPGA representative to inquire about a platform suitable to run this hardware example

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