25G Ethernet Intel® Arria® 10 FPGA IP Design Example User Guide

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ID 683833
Date 12/14/2020
Public
Document Table of Contents
Document Table of Contents x
1. 25G Ethernet Intel FPGA IP Quick Start Guide 2. Design Example Description 3. 25G Ethernet Intel® Arria® 10 FPGA IP Design Example User Guide Archives 4. Document Revision History for 25G Ethernet Intel® Arria® 10 FPGA IP Design Example User Guide
1. 25G Ethernet Intel FPGA IP Quick Start Guide x
1.1. Design Example Directory Structure 1.2. Simulation Design Example Components 1.3. Hardware Design Example Components 1.4. Generating the Design Example 1.5. Simulating the 25G Ethernet Intel FPGA IP Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the 25G Ethernet Intel FPGA IP Hardware Design Example
2. Design Example Description x
2.1. Design Example Behavior 2.2. Design Example Interface Signals 2.3. 25G Ethernet Intel FPGA IP Design Example Registers
1. 25G Ethernet Intel FPGA IP Quick Start Guide
2. Design Example Description
3. 25G Ethernet Intel® Arria® 10 FPGA IP Design Example User Guide Archives
4. Document Revision History for 25G Ethernet Intel® Arria® 10 FPGA IP Design Example User Guide

4. Document Revision History for 25G Ethernet Intel® Arria® 10 FPGA IP Design Example User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2020.12.14 20.4 19.4.1
  • Renamed document title to 25G Ethernet Intel® Arria® 10 FPGA IP Design Example User Guide.
  • Updated Figure: Example Design Tab in the 25G Ethernet Intel FPGA IP Parameter Editor.
  • Removed step related to hardware board selection in Generating the Design Example.
  • Added IOPLL to components list and figure in Hardware Design Example Components.
  • Added entry for .sdc file in Design Example Directory Structure and noted it can be used as a starting point to develop the .sdc file for any other 25G Ethernet Intel FPGA IP design.
  • Updated Design Example Description to provide individual bit information about user_led[7:0].
  • Clarified that the testbench does not provide a full verification environment. Refer to Design Example Description
  • Added section 25G Ethernet Intel® Arria® 10 FPGA IP Design Example User Guide Archives.
Date Release Changes
2017.11.08 16.1 Added link to KDB Answer that provides workaround for potential jitter on Intel® Arria® 10 devices due to cascading ATX PLLs in the IP core. Refer to Generating the Design Example and Compiling and Configuring the Design Example in Hardware.
Note: This design example user guide has not been updated to reflect minor changes in design generation in Intel® Quartus® Prime releases later than the Intel® Quartus® Prime software release v16.1.
2016.10.31 16.1 Initial release.
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