25G Ethernet Intel® Arria® 10 FPGA IP Design Example User Guide

ID 683833
Date 12/14/2020
Public

1.2. Simulation Design Example Components

Figure 3.  25G Ethernet Intel FPGA IP Simulation Design Example Block Diagram

The simulation design example top-level test file is basic_avl_tb_top.sv This file instantiates and connects an ATX PLL. It includes a task, send_packets_25g_avl, to send and receive 10 packets.

Table 1.   25G Ethernet Intel FPGA IP Core Testbench File Descriptions
File Name Description
Testbench and Simulation Files
basic_avl_tb_top.sv Top-level testbench file. The testbench instantiates the DUT and runs Verilog HDL tasks to generate and accept packets.
Testbench Scripts
run_vsim.do The ModelSim script to run the testbench.
run_vcs.sh The Synopsys VCS script to run the testbench.
run_ncsim.sh The Cadence NCSim script to run the testbench.
run_xcelium.sh The Cadence Xcelium* script to run the testbench.

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