25G Ethernet Intel® Arria® 10 FPGA IP Design Example User Guide

ID 683833
Date 12/14/2020

1.3. Hardware Design Example Components

Figure 4.  25G Ethernet Intel FPGA IP Hardware Design Example High Level Block Diagram
The 25G Ethernet Intel FPGA IP hardware design example includes the following components:
  • 25G Ethernet Intel FPGA IP core.
  • Client logic that coordinates the programming of the IP core and packet generation.
  • ATX PLL to drive the device transceiver channel.
  • IOPLL to generate a 100 MHz clock from a 50 MHz input clock to the hardware design example.
  • JTAG controller that communicates with the System Console. You communicate with the client logic through the System Console.
Table 2.   25G Ethernet Intel FPGA IP Core Hardware Design Example File Descriptions

File Names


eth_ex_25g.qpf Quartus Prime project file
eth_ex_25g.qsf Quartus project settings file
eth_ex_25g.sdc Synopsys Design Constraints file. You can copy and modify this file for your own 25G Ethernet Intel FPGA IP design.
eth_ex_25g.v Top-level Verilog HDL design example file
common/ Hardware design example support files

Main file for accessing System Console