25G Ethernet Intel® Arria® 10 FPGA IP User Guide

ID 683639
Date 3/29/2021
Document Table of Contents

1. About the 25G Ethernet Intel FPGA IP

Updated for:
Intel® Quartus® Prime Design Suite 21.1
IP Version 19.4.0

The 25G Ethernet Intel FPGA IP implements the 25G & 50G Ethernet Specification, Draft 1.6 from the 25 Gigabit Ethernet Consortium and the IEEE 802.3by 25Gb Ethernet specification. The IP includes an option to support unidirectional transport as defined in Clause 66 of the IEEE 802.3-2012 Ethernet Standard. The MAC client side interface for the 25G Ethernet Intel FPGA IP is a 64-bit Avalon® streaming interface. It maps to one 25.78125 Gbps transceiver. The IP optionally includes the IEEE 802.3-2018 Clause 108 Reed-Solomon forward error correction (RS-FEC) for support of IEEE802.3-2018 Clause 107 25GBASE-R PCS. IEEE 802.3 Clause 73 Auto-Negotiation and IEEE 802.3 Clause 74 CR/KR-FEC are not supported. Transceiver interface to 25GBASE-SR optical Physical Medium Dependent (PMD) transceiver is supported.

The IP core provides standard media access control (MAC) and physical coding sublayer (PCS), RS-FEC, and PMA functions shown in the following block diagram. The PHY comprises the PCS, optional RS-FEC, and PMA.

Figure 1.  25G Ethernet Intel FPGA IP MAC and PHY IP Clock Diagram

The following block diagram shows an example of a network application with 25G Ethernet Intel FPGA IP MAC and PHY.

Figure 2. Example Network Application