1. About the 25G Ethernet Intel FPGA IP 2. Getting Started 3. 25G Ethernet Intel FPGA IP Parameters 4. Functional Description 5. Reset 6. Interfaces and Signal Descriptions 7. Control, Status, and Statistics Register Descriptions 8. Debugging the Link 9. 25G Ethernet Intel® Arria® 10 FPGA IP User Guide Archive 10. Document Revision History for the 25G Ethernet Intel® Arria® 10 FPGA IP User Guide
2.5.3. Handling Potential Jitter in Intel® Arria® 10 Devices
The RX path in the 25G Ethernet Intel FPGA IP core includes cascaded PLLs. Therefore, the IP core clocks might experience additional jitter in Intel® Arria® 10 devices.
Refer to the KDB Answer How do I compensate for the jitter of PLL cascading or non-dedicated clock path for Arria 10 PLL reference clock? for a workaround you should apply to the IP core, in your design.
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