25G Ethernet Intel® Arria® 10 FPGA IP User Guide

ID 683639
Date 3/29/2021
Document Table of Contents

6.2. RX MAC Interface to User Logic

The RX MAC provides an Avalon® streaming interface to the FPGA fabric. The datapath consists of a single 64-bit word.
Table 13.   Avalon® Streaming RX Datapath All interface signals are clocked by the clk_rxmac clock.




clk_rxmac Output Clock for the RX MAC. Recovered from the incoming data. This clock is guaranteed stable when rx_pcs_ready is asserted. The frequency of this clock is 390.625 MHz. All RX MAC interface signals are synchronous to clk_rxmac .
l1_rx_data[63:0] Output

Data output from the MAC. Bit[63] is the MSB and bit[0] is the LSB. Bytes are read in the usual left to right order. The IP core reverses the byte order to meet the requirements of the Ethernet standard.

l1_rx_valid Output When asserted, indicates that l1_rx_data[63:0] is driving valid data.

If you turn off Enable RS-FEC , the IP core asserts this signal continuously between the assertions of l1_tx_startofpacket and l1_tx_endofpacket for the same packet. However, if you turn on Enable RS-FEC , the IP core drives IDLE cycles during alignment marker cycles.

l1_rx_startofpacket Output

When asserted, indicates the first byte of a frame.

l1_rx_endofpacket Output When asserted, indicates the last data byte of a frame, before the frame check sequence (FCS). In CRC pass-through mode, it is the last byte of the FCS. The packet can end at any byte position.
l1_rx_empty[2:0] Output Specifies the number of empty bytes when l1_rx_endofpacket is asserted.

The packet can end at any byte position. The empty bytes are the low-order bytes.

l1_rx_error[5:0] Output

When asserted in the same cycle as l1_rx_endofpacket, indicates the current packet should be treated as an error packet. The 6 bits of l1_rx_error specify the following errors:

  • l1_rx_error[5]: Unused.
  • l1_rx_error[4]: Payload length error. If the length field is <1535 bytes (0x600 bytes), the received payload length is less than what is advertised in the payload length field.
  • l1_rx_error[3]: Oversized frame. The frame size is greater than the value specified in the MAX_RX_SIZE_CONFIG register.
  • l1_rx_error[2]: Undersized frame – The frame size is less than 64 bytes. Frame size = header size + payload size.
  • l1_rx_error[1]: CRC Error. The computed CRC value differs from the received CRC.
  • l1_rx_error[0]: Malformed packet. The packet is terminated with a non-terminate control character. When this bit is asserted, l1_rx_error[1] is also asserted.
l1_rxstatus_valid Output When asserted, indicates that l1_rxstatus_data is driving valid data.
l1_rxstatus_data[39:0] Output

Specifies information about the received frame. The following fields are defined:

  • Bit[39]: When asserted, indicates a PFC frame
  • Bit[38]: When asserted, indicates a unicast frame
  • Bit[37]: When asserted, indicates a multicast frame
  • Bit[36]: When asserted, indicates a broadcast frame
  • Bit[35]: When asserted, indicates a pause frame
  • Bit[34]: When asserted, indicates a control frame
  • Bit[33]: When asserted, indicates a VLAN frame
  • Bit[32]: When asserted, indicates a stacked VLAN frame
  • Bits[31:16]: Specifies the frame length from the first byte of the destination address to the last bye of the FCS
  • Bits[15:0]: Specifies the payload length
pause_receive_rx[FCQN-1:0] Output Each bit of pause_receive_rx[FCQN-1:0] indicates that the corresponding queue is being paused.
Figure 32.  25G Ethernet Intel FPGA IP MAC to Client Avalon® Streaming Interface l1_rx_data reception order is highest byte to lowest byte. The first byte of the destination address is on l1_rx_data[65:56] , 0xfbe4 . . . in this timing diagram.